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| 1. description the m37212m6-xxxsp/fp, m37212m4/m8-xxxsp are single-chip microcomputers designed with cmos silicon gate technology. they have a osd, i 2 c-bus interface, and pwm, so it is useful for a chan- nel selection system for tv. the feature of the m37212efsp/fp are similar to those of the m37212m6-xxxsp/fp except that these chips have a built-in prom which can be written electrically. the differences between the m37212m6-xxxsp/fp and m37212m4/m8-xxxsp are the rom size and the ram size as shown below. accordingly, the following de- scriptions will be for m37212m6-xxxsp/fp unless otherwise noted. 2. features l number of basic instructions ..................................................... 71 l memory size rom............... ......... 16k bytes (m37212m4-xxxsp) 24k bytes (m37212m6-xxxsp/fp) 32k bytes (m37212m8-xxxsp) 62k bytes (m37212efsp/fp) ram ......................... 320 bytes (m37212m4-xxxsp) 384 bytes (m37212m6-xxxsp/fp) 576 bytes (m37212m8-xxxsp) 1280 bytes (m37212efsp/fp) (*rom correction memory included) l the minimum instruction execution time ......................................... 0.5 m s (at 8 mhz oscillation frequency) l power source voltage .................................................. 5 v 10 % l subroutine nesting maximum 96 levels (m37212m4/m8-xxxsp, m37212m6-xxxsp/fp) maximum 128 levels (m37212efsp/fp) l interrupts ........................................................ 14 types, 14 vectors l 8-bit timers ................................................................................... 4 l programmable i/o ports (ports p0, p1 0 Cp1 4 , p2, p3 0 , p3 1, p4 0, p4 1 ) ............................. 25 l input ports (ports p1 5 Cp1 7 , p3 2 Cp3 7 , p4 2 ) ............................... 10 l output ports (ports p5 2 Cp5 5, p6 0 Cp6 3 ) ....................................... 8 l 12 v withstand ports .................................................................. 12 l led drive ports ............................................................................ 4 l serial i/o ............................................................. 8-bit 5 1 channel l multi-master i 2 c-bus interface ............................... 1 (2 systems) l a-d comparator (6-bit resolution) ................................. 8 channels l pwm output circuit .......................................... 14-bit 5 1, 8-bit 5 8 l power dissipation .............................................................. 165 mw (at 8 mhz oscillation frequency, v cc =5.5v, at osd display) l rom correction function ................................................. 2 vectors note: only m37212m8-xxxsp and m37212efsp/fp have rom correction function. single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 l osd function display characters ................................... 24 characters 5 2 lines (it is possible to display 3lines or more by software) kinds of characters ........................................................ 256 kinds character display area .............................................. 12 5 16 dots kinds of character sizes ..................................................... 3 kinds kinds of character colors .................................. 8 colors (r, g, b) coloring unit ................... character, character background, raster display position ............................................................................. horizontal: 64 levels vertical: 128 levels attribute .............................................................................. border 3. application tv
2 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 table of contents 1. description .......................................................................... 1 2. feautures ............................................................................. 1 3. application ............................................................................ 1 4. pin configuration .............................................................. 3 5. functional block diagram ............................................. 5 6. performance overview ................................................... 6 7. pin description ................................................................... 8 8. functional description ................................................. 12 8.1 central processing unit (cpu) .................... 12 8.2 memory .................................................................. 13 8.3 interrupts ........................................................... 19 8.4 timers ..................................................................... 24 8.5 serial i/o ................................................................ 27 8.6 multi-master i 2 c-bus interface .................... 31 8.7 pwm output circuit .......................................... 44 8.8 a-d comparator .................................................. 49 8.9 rom correction function ............................. 51 8.10 osd functions ................................................... 52 8.10.1 display position ....................................... 56 8.10.2 character size ......................................... 60 8.10.3 clock for osd .......................................... 62 8.10.4 memory for osd ...................................... 63 8.10.5 color register .......................................... 66 8.10.6 border ...................................................... 68 8.10.7 multiline display ....................................... 69 8.10.8 osd output pin control .......................... 70 8.10.9 raster coloring function ......................... 71 8.11. software runaway detect function ...... 72 8.12. reset circuit .................................................... 73 8.13. clock generating circuit ........................... 74 8.14. display oscillation circuit ........................ 75 8.15. auto-clear circuit ......................................... 75 8.16. addressing mode ............................................ 75 8.17. machine instructions ................................... 75 9. programming notes ........................................................ 75 10. absolute maximum ratings ......................................... 76 11. recommended operating conditions ..................... 76 12. electric characteristics .......................................... 77 13. a-d comparison characteristics ............................. 79 14. multi-master i 2 c-bus bus line characteristics ........... 79 15. prom programming method ....................................... 80 16. data required for mask orders .............................. 81 17. mask confirmation form ............................................. 82 18. mark specification form ............................................. 91 19. one time prom versions m37212efsp/fp marking .... 93 20. appendix ............................................................................. 94 21. package outline ........................................................... 117 3 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 p 4 1 / s c l k / a - d 6 x o u t h s y n c v s y n c p 6 0 / p w m 0 p 6 1 / p w m 1 p 6 2 / p w m 2 p 6 3 / p w m 3 p 0 0 / p w m 4 p 0 1 / p w m 5 p 4 0 / s o u t ( / i n ) / a - d 7 d a p 3 5 / i n t 2 / a - d 4 p 3 4 / i n t 1 p 3 3 / t i m 3 p 3 2 / t i m 2 p 2 4 p 2 5 c n v s s x i n v s s p 5 2 / r p 5 3 / g p 5 4 / b p 5 5 / o u t 1 p 2 0 p 2 1 p 2 2 p 1 0 / o u t 2 / a - d 8 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 p 1 5 / i n t 3 / a - d 1 p 1 6 / a - d 2 p 3 0 p 3 1 r e s e t o s c 1 / p 3 6 o s c 2 / p 3 7 v c c p 1 7 / a - d 3 p 0 2 / p w m 6 p 0 3 / p w m 7 p 4 2 / s i n / a - d 5 p 2 6 p 2 7 p 2 3 p 0 4 p 0 5 p 0 6 p 0 7 2 2 2 3 2 4 2 5 2 6 3 1 3 0 2 9 2 8 2 7 m 3 7 2 1 2 m 4 / m 6 / m 8 - x x x s p , m 3 7 2 1 2 e f s p 4. pin configuration outline 52p4b fig. 4.1 pin configuration 1 (top view) 4 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 p 0 7 5 5 4 3 p 1 0 / o u t 2 / a - d 8 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 p 1 5 / i n t 3 / a - d 1 p 1 6 / a - d 2 p 3 0 p 3 1 r e s e t o s c 1 / p 3 6 o s c 2 / p 3 7 v c c p 1 7 / a - d 3 h s y n c v s y n c p 6 0 / p w m 0 p 6 1 / p w m 1 p 6 2 / p w m 2 p 6 3 / p w m 3 p 0 0 / p w m 4 p 0 1 / p w m 5 p 0 2 / p w m 6 p 0 3 / p w m 7 x o u t v s s p 4 1 / s c l k / a - d 6 p 4 0 / s o u t ( / i n ) / a - d 7 d a p 3 5 / i n t 2 / a - d 4 p 3 4 / i n t 1 p 3 3 / t i m 3 p 3 2 / t i m 2 p 2 4 p 2 5 p 4 2 / s i n / a - d 5 c n v s s x i n p 2 6 p 2 7 p 5 2 / r p 5 3 / g p 5 4 / b p 5 5 / o u t 1 p 2 0 p 2 1 p 2 2 p 2 3 p 0 4 p 0 5 p 0 6 2 8 4 0 3 9 3 7 3 8 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 7 2 6 2 5 5 1 4 1 4 4 4 5 4 6 4 7 4 8 5 0 5 8 5 2 5 9 5 7 5 6 6 0 6 1 6 3 6 2 4 2 4 9 n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c 8 1 2 3 4 5 6 7 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 4 2 3 2 2 2 1 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 m 3 7 2 1 2 m 6 - x x x f p , m 3 7 2 1 2 e f f p n c 6 4 5 4 5 3 outline 80p6n-a nc : unconnected fig. 4.2 pin configuration 2 (top view) 5 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 5. functional block diagram fig. 5.1 functional block diagram of m37212 out1 clock input clock output x in x out reset input v cc v ss cnv ss clock output for display input ports p3 6, p3 7 osc1 osc2 clock input for display int2 int1 p5 (4) b g r h sync v sync a-d comparator 14-bit pwm circuit 8-bit pwm circuit accumulator a (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 instruction register (8) instruction decoder control signal crt circuit stack pointer s (8) index register y (8) index register x (8) processor status register ps (8) 8-bit arithmetic and logical unit rom program counter pc l (8) program counter pc h (8) ram data bus clock generating circuit reset output ports p5 2 ?5 5 address bus si/o(8) s in s clk s out(/in) int3 4142 434410 9 8 7 i/o port p0 33 34353637383940 p1 (8) i/o ports p1 0 ?1 4 2221201945 464748 p2 (8) i/o port p2 i/o ports p3 0 , p3 1 18 3132 14 p3 (6) multi-master i c-bus interface p0 (8) sda scl 49 50 51 52 2 1 25 24 30 27 26 23 29 28 ( ) timing output out2 da 2 1516 17 p4 (3) 1112 13 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 pwm7 pwm6 input ports p1 5 ?1 7 input ports p3 2 ?3 5 p6 (4) output ports p6 0 ?6 3 6 5 4 3 i/o ports p4 0 , p4 1 input port p4 2 output for display 6 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 6. performance overview table 6.1 performance overview parameter functions number of basic instructions 71 number of basic instructions 0.5 m s (the minimum instruction execution time, at 8 mhz oscillation fre quency) instruction execution time 8 mhz (maximum) memory size rom m37212m4-xxxsp 16k bytes m37212m6-xxxsp/fp 24k bytes m37212m8-xxxsp 32k bytes m37212efsp/fp 62k bytes ram m37212m4-xxxsp 320 bytes m37212m6-xxxsp/fp 384 bytes m37212m8-xxxsp 576 bytes (rom correction memory included) m37212efsp/fp 1280 bytes (rom correction memory included) osd rom 8 k bytes osd ram 96 bytes input/output ports p0 i/o 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins) p1 0 Cp1 4 i/o 5-bit 5 1 (cmos input/output output structure, however, n-channel open- drain output structure, when p1 1 Cp1 4 are used as multi-master i 2 c-bus interface, can be used as osd output, a-d input, multi-master i 2 c-bus interface) p1 5 Cp1 7 input 3-bit 5 1 (can be used as int input pin, a-d input pins) p2 0 Cp2 7 i/o 8-bit 5 1 (cmos input/output structure) p3 0 , p3 1 i/o 2-bit 5 1 (cmos input/output structure) p3 2 Cp3 7 input 6-bit 5 1 (can be used as external clock input pins, int input pins, osd display clock i/o pins, a-d input pins) p4 0 , p4 1 i/o 2-bit 5 1 (n-channel open-drain output structure, can be used as serial i/o pins, a-d input pins) p4 2 input 1-bit 5 1(can be used as serial input pin, a-d input pin) p5 2 Cp5 5 output 4-bit 5 1 (cmos output structure, can be used as osd output pins) p6 0 Cp6 3 output 4-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins) serial i/o 8-bit 5 1 multi-master i 2 c-bus interface 1 (2 systems) a-d comparator 8 channels (6-bit resolution) pwm output circuit 14-bit 5 1, 8-bit 5 8 timers 8-bit timer 5 4 subroutine nesting 96 levels (maximum) interrupt <14 sources> int external interrupt 5 3, internal timer interrupt 5 4, serial i/o interrupt 5 1, osd interrupt 5 1, multi-master i 2 c-bus interface interrupt 5 1, f(x in )/ 4096 interrupt 5 1, v sync interrupt 5 1, brk interrupt 5 1, reset 5 1 clock generating circuit 2 built-in circuits (externally connected a ceramic resonator or a quartz- crystal oscillator) 7 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 parameter functions osd display number of display characters 24 characters 5 2 lines function dot structure 12 5 16 dots kinds of characters 254 kinds kinds of character sizes 3 kinds character font coloring 1 screen: 8 kinds (per character unit) display position horizontal: 64 levels, vertical: 128 levels power source voltage 5 v 10 % power dissipation osd on 165 mw typ. (at oscillation frequency f(x in ) = 8 mhz, f osc = 8 mhz) osd off 110 mw typ. (at oscillation frequency f(x in ) = 8 mhz) in stop mode 1.65 mw (maximum) operating temperature range C10 c to 70 c device structure cmos silicon gate process package m37212m4/m6/m8-xxxsp, m37212efsp 52-pin plastic molded sdip m37212m6-xxxfp, m37212efsp 80-pin plastic molded qfp table 6.2 performance overview (continued) 8 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 pin name input/ functions output v cc , power source apply voltage of 5 v 10 % to (typical) v cc , and 0 v to v ss . v ss. cnv ss cnv ss this is connected to v ss . ______ reset reset input input to enter the reset state, the reset input pin must be kept at a l for 2 m s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this l condition should be maintained for the required time. x in clock input input this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out clock output output x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. p0 0 /pwm4C i/o port p0 i/o port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually p0 3 /pwm7, programmed as input or output. at reset, this port is set to input mode. the output structure p0 4 Cp0 7 is n-channel open-drain output. (see note) pwm output output pins p0 0 Cp0 3 are also used as pwm output pins pwm4Cpwm7 respectively. the output structure is n-channel open-drain output. p1 0 /out2/ i/o port p1 i/o port p1 0 Cp1 4 are a 5-bit i/o port and has basically the same functions as port p0. the a-d8, output structure is cmos output. p1 1 /scl1, osd output output pins p1 0 is also used as osd output pin out2. the output structure is cmos output. p1 2 /scl2, multi-master i/o pins p1 1 Cp1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master p1 3 /sda1, i 2 c-bus interface i 2 c-bus interface is used. the output structure is n-channel open-drain output. p1 4 /sda2, analog input input p1 0 pin is also used as analog input pin a-d8. p1 5 /int3/ input port p1 input port p1 5 Cp1 7 are a 3-bit input port and has basically the same functions as port p0. a-d1, analog input input pins p1 5 Cp1 7 are also used as analog input pins a-d1 to a-d3 respectively. p1 6 /a-d2, external interrupt input p1 5 pin is also used as int external interrupt input pin int3. p1 7 /a-d3 input p2 0 Cp2 7 i/o port p2 i/o port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. (see note) p3 0 , p3 1 i/o port p3 i/o ports p3 0 , p3 1 are a 2-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. p3 2 /tim2, input port p3 input ports p3 2 Cp3 7 are a 6-bit input port and has basically the same functions as port p0. p3 3 /tim3, external clock input input pins p3 2 , p3 3 are also used as external clock input pins tim2, tim3 respectively. p3 4 /int1, external interrupt input pins p3 4 , p3 5 are also used as int external interrupt input pins int1, int2 respectively. p3 5 /int2/ input a-d4, analog input input p3 5 pin is also used as analog input pin a-d4. p3 6 /osc1, clock input for input p3 6 pin is also used as osd display clock input pin osc1. p3 7 /osc2 osd display clock output for output p3 7 pin is also used as osd display clock output pin osc2. the output structure is cmos osd display output. 7. pin description table 7.1 pin description 9 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 note : port pi (i = 0 to 3) has the port pi direction register which can be used to program each bit as an input (0) or an output ( 1). the pins programmed as 1 in the direction register are output pins. when pins are programmed as 0, they are input pins. when pins are programmed as outpu t pins, the output data are written into the port latch and then output. when data is read from the output pins, the output pin level is not read but the d ata of the port latch is read. this allows a previously-output value to be read correctly even if the output l voltage has risen, for example, because a light em itting diode was directly driven. the input pins are in the floating state, so the values of the pins can be read. when data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. pin name input/ functions output p4 0 /s out(/in) / i/o port p4 i/o ports p4 0 , p4 1 are a 2-bit i/o port and has basically the same functions as port p0. the a-d7, output structure is n-channel open-drain output. p4 1 /s clk / serial i/o data i/o pin p4 0 is also used as serial i/o data input/output pin s out(/in) . the output structure is n- a-d6, input/output channel open-drain output. serial i/o synchronizing i/o pin p4 1 is also used as serial i/o synchronizing clock input/output pin s clk . the output clock input/output structure is n-channel open-drain output. analog input pin input pin p4 0 , p4 1 are also used as analog input pins a-d7, a-d6 respectively. p4 2 /s in / input port p4 input port p4 2 is a 1-bit input port and has basically the same functions as port p0. a-d5, serial i/o data input pin p4 2 is also used as serial i/o data input pin s in . input analog input input pin p4 2 is also used as analog input pin a-d5. p5 2 /r, output port p5 output ports p5 2 Cp5 5 are a 4-bit output port and has basically the same functions as port p0. the p5 3 /g, output structure is cmos output. p5 4 /b, osd output output pins p5 2 Cp5 5 are also used as osd output pins r, g, b, out1 respectively. the output p5 5 /out1 structure is cmos output. p6 0 pwm0C output port p6 output ports p6 0 Cp6 3 are a 4-bit i/o port and has basically the same functions as port p0. the p6 3 /pwm3 output structure is n-channel open-drain output. pwm output output pins p6 0 Cp6 3 are also used as pwm output pins pwm0Cpwm3 respectively. the output structure is n-channel open-drain output. h sync h sync input input this is a horizontal synchronizing signal input for osd. v sync v sync input input this is a vertical synchronizing signal input for osd. da da output output this is a 14-bit pwm output pin. table 7.2 pin description (continued) 10 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 7.1 i/o pin block diagram (1) cmos output ports p1 0 , p2, p3 0 , p3 1 note : port p1 0 is also used as out2/ a-d8. n-channel open-drain output ports p4 0 , p4 1 note : each port is also used as follows : p4 0 : s out(/in) /a-d7 p4 1 : s clk /a-d6 n-channel open-drain output port p0 note : each port is also used as follows : p0 0 Cp0 3 : pwm4Cpwm7 port p0 data bus direction register port latch ports p1 0 , p2, p3 0 , p3 1 data bus direction register port latch ports p4 0, p4 1 data bus direction register port latch s in , s clk ports p1 1 ?1 4 data bus direction register port latch i 2 c-bus clock i 2 c-bus data bsel0 bsel1 scl1, scl2, sda1, sda2 n-channel open-drain output cmos output ports p1 1 Cp1 4 notes 1: each port is also used as follows : p1 1 : scl1 p1 2 : scl2 p1 3 : sda1 p1 4 : sda2 2: the output structure of ports p1 1 C p1 4 is n-channel open-drain output when using as multi-master i 2 c- bus interface (it is the same with ports p4 0 and p4 1 ). 11 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 ports p1 6 , p1 7 note : each port is also used as follows : p1 6 : a-d2 p1 7 : a-d3 schmidt input ports p1 5 , p3 2 Cp3 7 , p4 2 note : each port is also used as follows : p1 5 : int3/a-d1 p3 2 : tim2 p3 3 : tim3 p3 4 : int1 p3 5 : int2/a-d4 p3 6 : osc1 p3 7 : osc2 p4 2 : s in /a-d5 fig. 7.2 i/o pin block diagram (2) n-chanel open drain output ports p6 0 Cp6 3 note : each port is also used as follows : p6 0 Cp6 3 : pwm0Cpwm3 cmos output ports d-a, r, g, b, out1, out2 note : each pin is also used as follows : r : p5 2 g : p5 3 b : p5 4 out1 : p5 5 out2 : p1 0 /a-d8 internal circuit d-a, r, g, b, out1 , out2 data bus ports p1 5 , p3 2 ?3 7 , p4 2 tim2, tim3, int1, int2, s in , int3 data bus ports p1 6 , p1 7 data bus ports p6 0 ?6 3 port latch h sync , v sync internal circuit schmidt input ports h sync , v sync 12 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8. functional description 8.1 central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 13 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.2 memory 8.2.1 special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. 8.2.2 ram ram is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 rom rom is used for storing user programs as well as the interrupt vector area. 8.2.4 osd ram ram for display is used for specifying the character codes and col- ors to display. 8.2.5 osd rom rom for display is used for storing character data. 8.2.6 interrupt vector area the interrupt vector area contains reset and interrupt vectors. 8.2.7 zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. 8.2.8 special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. 8.2.9 rom correction memory (ram) this is used as the program area for rom correction. note: only m37212m8-xxxsp and m37212efsp/fp have rom correction memory. fig. 8.2.1 memory map (m37212m4/m8-xxxsp, m37212m6-xxxsp/fp) 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 6 b 7 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 0 6 0 0 1 6 1 1 f f f 1 6 1 f f f f 1 6 o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) 0 1 7 f 1 6 0 1 b f 1 6 1 0 0 0 0 1 6 o s d r o m ( 8 k b y t e s ) s f r a r e a i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e z e r o p a g e n o t e : r e f e r t o t a b l e 8 . 1 0 . 3 o s d r a m . 0 1 0 0 1 6 0 0 b f 1 6 n o t u s e d a 0 0 0 1 6 n o t u s e d c 0 0 0 1 6 n o t u s e d m 3 7 2 1 2 m 6 - x x x s p / f p r a m ( 3 8 4 b y t e s ) m 3 7 2 1 2 m 4 - x x x s p r a m ( 3 2 0 b y t e s ) m 3 7 2 1 2 m 6 - x x x s p / f p r o m ( 2 4 k b y t e s ) m 3 7 2 1 2 m 4 - x x x s p r o m ( 1 6 k b y t e s ) n m 3 7 2 1 2 m 4 / m 8 - x x x s p , m 3 7 2 1 2 m 6 - x x x s p / f p 14 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.2.2 memory map (m37212m8-xxxsp, m37212efsp/fp) 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 6 b 7 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 0 6 0 0 1 6 1 1 f f f 1 6 1 f f f f 1 6 o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) m 3 7 2 1 2 e f s p r a m ( 1 2 8 0 b y t e s ) 0 8 0 0 1 6 1 0 0 0 0 1 6 o s d r o m ( 8 k b y t e s ) 0 2 c 0 1 6 s f r a r e a i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e z e r o p a g e n o t u s e d n o t e : r e f e r t o t a b l e 8 . 1 0 . 3 o s d r a m 0 2 1 7 1 6 0 2 1 b 1 6 r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 0 1 0 0 1 6 0 0 b f 1 6 0 5 f f 1 6 n o t u s e d 0 2 e 0 1 6 m 3 7 2 1 2 m 8 - x x x s p r a m ( 5 7 6 b y t e s ) 0 1 f f 1 6 n o t u s e d n o t u s e d 0 3 3 f 1 6 2 p a g e r e g i s t e r m 3 7 2 1 2 e f s p r o m ( 6 2 k b y t e s ) m 3 7 2 1 2 m 8 - x x x s p r o m ( 3 2 k b y t e s ) 8 0 0 0 1 6 n m 3 7 2 1 2 m 8 - x x x s p , m 3 7 2 1 2 e f s p / f p 15 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.2.3 memory map of special function register (sfr) (1) n s f r a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) d 0 1 6 d 1 1 6 d 2 1 6 d 3 1 6 d 4 1 6 d 5 1 6 d 6 1 6 d 7 1 6 d 8 1 6 d 9 1 6 d a 1 6 d b 1 6 d c 1 6 d d 1 6 d e 1 6 d f 1 6 c 0 1 6 c 1 1 6 c 2 1 6 c 3 1 6 c 4 1 6 c 5 1 6 c 6 1 6 c 7 1 6 c 8 1 6 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 c a 1 6 a d d r e s s p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( d 5 ) d a - h r e g i s t e r ( d a - h ) d a - l r e g i s t e r ( d a - l ) p w m 0 r e g i s t e r ( p w m 0 ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( d 1 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m 2 r e g i s t e r ( p w m 2 ) p w m 3 r e g i s t e r ( p w m 3 ) p w m 4 r e g i s t e r ( p w m 4 ) p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) b 7 b 0 b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t ? 0 0 1 6 b 7 b 0 ? 0 0 1 6 ? 0 0 1 6 0? ? ? ?00 s e r i a l i / o m o d e r e g i s t e r ( s m ) s e r i a l i / o r e g i s t e r ( s i o ) 0 0 1 6 p o r t p 6 ( p 6 ) p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) 0 p 5 2 s e l 00 p 5 3 s e l p 5 4 s e l p 5 5 s e l p 5 2 p 5 3 p 5 4 p 5 5 p 3 1 dp 3 0 d ? 0 ? 0 0 0 ?? 0 p w 0 p w 1 p w 2 p w 3 p w 4 p w 5 p w 6 p w 7 p n 2 p n 3 p n 4 ? 0 0 ? ? ? ? ? ? ? ? ? ? 0 0 1 6 0 0 1 6 0 f 1 6 s a d 0 s a d 1 s a d 2 s a d 3 s a d 4 s a d 5 s a d 6 r b w l r b a d 0 a a s a l p i n b b t r x m s t b c 0 b c 1 b c 2 e s o a l s b s e l 0 b s e l 1 1 0 b i t s a d d 1 d 2 d 3 d 4 d 5 d 6 d 7d 0 ? ? 0 0 1 6 0 0 1 6 s m 0 s m 1 s m 2 s m 3 s m 5 s m 6 0 c c r 0 c c r 1 c c r 2 c c r 3 c c r 4 a c k f a s t m o d e a c k b i t ? 0 0 1 6 0 0 1 6 ? 0 0 ? 0 0 0 1 0 : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( d 4 ) p n 0 p n 1 p 4 1 dp 4 0 d p 4 1p 4 0 p 6 1p 6 0 p 6 2 0 ? 0 0 0 ?? 0 0 0 1 6 0 f 1 6 ? p 6 3 11 1 1 16 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.2.4 memory map of special function register (sfr) (2) f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e 7 1 6 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 c r t c o n t r o l r e g i s t e r ( c c ) c r t p o r t c o n t r o l r e g i s t e r ( c r t p ) a - d m o d e r e g i s t e r ( a d m ) a - d c o n t r o l r e g i s t e r ( a d c ) t i m e r 1 ( t 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 ( c v 2 ) c o l o r r e g i s t e r 0 ( c o 0 ) c o l o r r e g i s t e r 1 ( c o 1 ) c h a r a c t e r s i z e r e g i s t e r ( c s ) b o r d e r s e l e c t i o n r e g i s t e r ( m d ) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h r ) v e r t i c a l p o s i t i o n r e g i s t e r 1 ( c v 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) p w m 5 r e g i s t e r ( p w m 5 ) i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) c o l o r r e g i s t e r 2 ( c o 2 ) c o l o r r e g i s t e r 3 ( c o 3 ) c r t c l o c k s e l e c t i o n r e g i s t e r ( c k ) c p u m o d e r e g i s t e r ( c m ) b 7 b 0 c c 0 c c 1 c c 2 t 3 4 m 0 c m 2 t m 1 r t m 2 r t m 3 r t m 4 r o s d r v s c r i t 3 r c k 0 m s r i t 1 r i t 2 r s 1 r t m 1 e t m 2 e t m 3 e t m 4 e o s d e v s c e i t 3 e i t 1 e i t 2 e s 1 e m s e b 7 b 0 f f 1 6 0 7 1 6 f f 1 6 0 7 1 6 ? ? ? 00 1 0 0 11 11 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 fc 1 6 0 0 1 6 0 0 1 6 0 0 1 6 p w m 6 r e g i s t e r ( p w m 6 ) p w m 7 r e g i s t e r ( p w m 7 ) i i c r r e3 r e4 h r 0 h r 1 h r 2 h r 3 h r 4 h r 5 c v 1 0 c s 1 0 c s 1 1 c s 2 0 c s 2 1 m d 1 0 m d 2 0 c c 7 v s y c r / g / b o u t 2 o p 5 o u t 1 o p 6h s y c a d m0 a d c0 0 0 1 6 0 00 0?0 ? 0 0 00 ??? ? 0 0 0 1 6 0 0 1 6 n s f r a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 i i c e 00 0 0 r e5 t 3 4 m 1 t 3 4 m 2 t 3 4 m 3 t 3 4 m 4 t 3 4 m 5 t 1 2 m 0 t 1 2 m 1 t 1 2 m 2 t 1 2 m 3 t 1 2 m 4 0 a d c1 a d c2 a d c3 a d c4 a d c5 a d m1 a d m2 a d m4 00 c k0 c k1 o p 7 c o 3 1 c o 3 2 c o 3 3 c o 3 5c o 3 4 c o 3 6 c o 3 7 c o 2 1 c o 2 2 c o 2 3 c o 2 5c o 2 4 c o 2 6 c o 2 7 c o 1 1 c o 1 2 c o 1 3 c o 1 5c o 1 4 c o 1 6 c o 1 7 c o 0 1 c o 0 2 c o 0 3 c o 0 5c o 0 4 c o 0 6 c o 0 7 c v 1 1 c v 1 2 c v 1 3 c v 1 4 c v 1 5 c v 1 6 c v 2 0 c v 2 1 c v 2 2 c v 2 3 c v 2 4 c v 2 5 c v 2 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 ? 00 000 0 0 0 0 1 6 ? 0 0 1 6 ? ?? ??? ? 0 ? ?? ??? ? 0 0000 ?00 0000 0 17 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.2.5 memory map of 2 page register area b 7b 0b 7b 0 2 1 7 1 6 2 1 8 1 6 2 1 9 1 6 2 1 b 1 6 2 1 a 1 6 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) r c r 1r c r 0 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 0 1 6 n 2 p a g e r e g i s t e r a r e a ( a d d r e s s e s 2 1 7 1 6 t o 2 1 b 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 n o t e : o n l y m 3 7 2 1 2 m 8 - x x x s p a n d m 3 7 2 1 2 e f s p / f p h a v e 2 p a g e r e g i s t e r . < b i t a l l o c a t i o n >< s t a t e i m m e d i a t e l y a f t e r r e s e t > 18 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.2.6 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i z c d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 < b i t a l l o c a t i o n >< s t a t e i m m e d i a t e l y a f t e r r e s e t > 19 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 8.3 interrupts interrupts can be caused by 14 different sources consisting of 4 ex- ternal, 8 internal, 1 software, and reset. interrupts are vectored inter- rupts with priorities as shown in table 8.3.1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, ? the contents of the program counter and processor status regis- ter are automatically stored into the stack. the interrupt disable flag i is set to 1 and the corresponding interrupt request bit is set to 0. a the jump destination address stored in the vector address enters the program counter. other interrupts are disabled when the interrupt disable flag is set to 1. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figures 8.3.2 to 8.3.6 show the interrupt-related registers. interrupts other than the brk instruction interrupt and reset are ac- cepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be set to 0 by a program, but not set to 1. the interrupt enable bit can be set to 0 and 1 by a program. reset is treated as a non-maskable interrupt with the highest priority. figure 8.3.1 shows interrupt control. 8.3.1 interrupt causes (1) v sync , osd interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the osd interrupt occurs after character block display to the crt is completed. (2) int1 to int3 external interrupts the int1 to int3 interrupts are external interrupt inputs, the sys- tem detects that the level of a pin changes from low to high or from high to low, and generates an interrupt request. the in- put active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00f9 16 ) : when this bit is 0, a change from low to high is detected; when it is 1, a change from high to low is detected. note that both bits are cleared to 0 at reset. (3) timers 1 to 4 interrupts an interrupt is generated by an overflow of timers 1 to 4. vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe9 16 , ffe8 16 ffe7 16 , ffe6 16 ffe5 16 , ffe4 16 ffdf 16 , ffde 16 interrupt source reset osd interrupt int2 external interrupt int1 external interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt multi-master i 2 c-bus interface interrupt int3 external interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable non-maskable table 8.3.1 interrupt vector addresses and priority 20 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. (5) f(x in )/4096 interrupt the f (x in )/4096 interrupt occurs regularly with a f(x in )/4096 pe- riod. set bit 0 of pwm output control register 1 to 0. (6) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (7) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 8.3.1 interrupt control interrupt request bi t interrupt enable bit interrupt disable flag i brk instruction reset interrupt request 21 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.3.2 interrupt request register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1 t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2 t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4 o s d i n t e r r u p t r e q u e s t b i t ( o s d r ) 5 v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( i i c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ] 1 6 ] r r r r r r r r i n t 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 3 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d fig. 8.3.3 interrupt request register 2 b 7b 6 b 5 b 4b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 1 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 2 r ) 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( m s r ) 5 , 6 7 f i x t h i s b i t t o 0 . 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . 0 0 ] 0 ] 0 ] 0 ] 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 6 ] r r r r r ? r w 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0r ? n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 22 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.3.4 interrupt control register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bn a m ef u n c t i o n s rw i n t e r r u p t c o n t r o l r e g i s t e r 1 0 t i m e r 1 i n t e r r u p t e n a b l e b i t ( t m 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 t i m e r 2 i n t e r r u p t e n a b l e b i t ( t m 2 e ) 2 t i m e r 3 i n t e r r u p t e n a b l e b i t ( t m 3 e ) 3 4 o s d i n t e r r u p t e n a b l e b i t ( o s d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 0 rw rw rw rw rw r 7 t i m e r 4 i n t e r r u p t e n a b l e b i t ( t m 4 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 v s y n c i n t e r r u p t e n a b l e b i t ( v s c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw a f t e r r e s e t i n t 3 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 3 e ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t e n a b l e b i t ( i i c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d w fig. 8.3.5 interrupt control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s i n t e r r u p t c o n t r o l r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 2 e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( m s e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d f i x t h i s b i t t o 0 . f i x t h e s e b i t s t o 0 . 0 00 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e i n d e t e r m i n a t e . a f t e r r e s e t 0 0 0 0 0 0 i n d e t e r m i n a t e rw rw rw rw rw r r w w r C 7 5 , 6 23 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.3.6 interrupt input polarity register b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) [ a d d r e s s 0 0 f 9 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 , 1 i n t 1 p o l a r i t y s w i t c h b i t ( r e 3 ) 20 0 3 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 4 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 5 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 6 0 7 0 0 i n t 2 p o l a r i t y s w i t c h b i t ( r e 4 ) i n t 3 p o l a r i t y s w i t c h b i t ( r e 5 ) n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . f i x t h i s b i t t o 0 . f i x t h i s b i t t o 0 . n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . r? r w r w r w r w r? r w 0 24 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.4 timers this microcomputer has 4 timers: timers 1 to 4. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 8.4.3. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4), the value is also set to a timer, simultaneously. the count value is decremented by 1. the timer interrupt request bit is set to 1 by a timer overflow at the next count pulse, after the count value reaches 00 16 . 8.4.1 timer 1 timer 1 can select one of the following count sources: ? f(x in )/16 ? f(x in )/4096 the count source of timer 1 is selected by setting bit 0 of timer 12 mode register 1 (address 00f4 16 ). timer interrupt request occurs at timer 1 overflow. 8.4.2 timer 2 timer 2 can select one of the following count sources: ? f(x in )/16 ? timer 1 overflow signal ? external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer 12 mode register (address 00f4 16 ). when timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 timer 3 timer 3 can select one of the following count sources: ? f(x in )/16 ? external clock from the h sync pin ? external clock from the tim3 pin the count source of timer 3 is selected by setting bits 5 and 0 of timer 34 mode register (address 00f5 16 ). timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 timer 4 timer 4 can select one of the following count sources: ? f(x in )/16 ? f(x in )/2 ? timer 3 overflow signal the count source of timer 3 is selected by setting bits 1 and 4 of timer 34 mode register (address 00f5 16 ). when timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. timer 4 interrupt request occurs at timer 4 overflow. at reset, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. the f(x in )/16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. however, the f(x in )/16 is not selected as the timer 3 count source. so set both bit 0 of timer 34 mode register (address 00f5 16 ) and bit 6 at address 00c7 16 to 0 before execution of the stp instruction (f(x in )/16 is selected as the timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the internal clock is connected. as a result of the above procedure, the program can start under a stable clock. the timer-related registers is shown in figures 8.4.1 and 8.4.2. 25 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.4.2 timer 34 mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) [ a d d r e s s 0 0 f 5 1 6 ] b a f t e r r e s e t rw t i m e r 3 4 m o d e r e g i s t e r 0 n a m e f u n c t i o n s t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 0 ) 0 rw 1 t i m e r 4 i n t e r n a l i n t e r r u p t c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 1 ) 0rw 2 3 t i m e r 3 c o u n t s t o p b i t ( t 3 4 m 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 4 c o u n t s t o p b i t ( t 3 4 m 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p 0 0 4 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 4 ) 0 : i n t e r n a l c l o c k s o u r c e 1 : f ( x i n ) / 2 0 5 t i m e r 3 e x t e r n a l c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 5 ) 0 : t i m 3 p i n i n p u t 1 : h s y n c p i n i n p u t 0 rw rw rw rw 0 : f ( x i n ) / 1 6 1 : e x t e r n a l c l o c k s o u r c e 0 : t i m e r 3 o v e r f l o w s i g n a l 1 : f ( x i n ) / 1 6 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r fig. 8.4.1 timer 12 mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r m o d e r e g i s t e r ( t 1 2 m ) [ a d d r e s s 0 0 f 4 1 6 ] b a f t e r r e s e t w t i m e r 1 2 m o d e r e g i s t e r 0 1 2 3 4 n a m e f u n c t i o n s t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t 1 2 m 0 ) 0 : f ( x i n ) / 1 6 1 : f ( x i n ) / 4 0 9 6 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t ( t 1 2 m 1 ) 0 : i n t e r r u p t c l o c k s o u r c e 1 : e x t e r n a l c l o c k f r o m t i m 2 p i n t i m e r 1 c o u n t s t o p b i t ( t 1 2 m 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 c o u n t s t o p b i t ( t 1 2 m 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 i n t e r n a l c o u n t s o u r c e s e l e c t i o n b i t 2 ( t 1 2 m 4 ) r 0 0 0 0 0 w r w r w r w r w r 0 : f ( x i n ) / 1 6 1 : t i m e r 1 o v e r f l o w 5 f i x t h i s b i t t o 0 . 0 w r 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r 0 26 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 timer 1 (8) 1/4096 1/2 1/8 timer 1 latch (8) 8 8 8 t12m0 t12m2 t12m4 t12m1 t12m3 timer 2 (8) timer 2 latch (8) 8 8 8 timer 3 (8) timer 3 latch (8) 8 8 8 timer 4 (8) timer 4 latch (8) 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request t34m0 t34m2 t34m5 t34m4 t34m3 t34m1 x in tim2 tim3 selection gate : connected to black colored side at reset t12m : timer 12 mode register t34m : timer 34 mode register ff 16 07 16 h sync reset stp instruction timer 3 interrupt request timer 4 interrupt request notes 1: ??pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used. fig. 8.4.3 timer block diagram 27 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.5 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in the clock synchronous mode. the serial i/o block diagram is shown in figure 8.5.1. the synchro- nous clock i/o pin (s clk ), data output pin (s out ), and data input pin (s in ) also functions as port p4. bit 3 of the serial i/o mode register (address 00dc 16 ) selects whether the synchronous clock is supplied internally or externally (from the s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 4, 16, 32, or 64. to use s in pin for serial i/o, set the corresponding bit of the port p2 direction regis- ter (address 00c5 16 ) to 0. fig. 8.5.1 serial i/o block diagram the operation of the serial i/o is described below. the operation of the serial i/o differs depending on the clock source; external clock or internal clock. 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate : connected to black colored side at reset. synchronization circuit frequency divider 1/8 1/4 1/16 sm1 sm0 serial i/o counter (8) sm5 : lsb msb s sm2 1/2 sm6 x in s in s out(/in) s clk 1/2 sm3 p4 0 latch p4 1 latch sm3 (address 00dd 16 ) note : when the data is set in the serial i/o register (address 00dd 16 ), the register functions as the serial i/o shift register. sm : serial i/o mode register (see note) 28 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 internal clock : the serial i/o counter is set to 7 during the write cycle into the serial i/o register (address 00dd 16 ), and the transfer clock goes high forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at high. at this time the interrupt request bit is set to 1. fig. 8.5.2 serial i/o timing (for lsb first) s y n c h r o n o u s c l o c k t r a n s f e r c l o c k s e r i a l i / o r e g i s t e r w r i t e s i g n a l s e r i a l i / o o u t p u t s o u t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ( s e e n o t e ) s e r i a l i / o i n p u t s i n n o t e : w h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e s o u t p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d . i n t e r r u p t r e q u e s t b i t i s s e t t o 1 external clock : the an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has been counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 1 mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 8.5.2. when using an exter- nal clock for transfer, the external clock must be held at high for initializing the serial i/o counter. when switching between an inter- nal clock and an external clock, do not switch during transfer. also, be sure to initialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing instructions, such as seb and clb. 2: when an external clock is used as the synchronous clock, write trans- mit data to the serial i/o register when the transfer clock input level is high. 29 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.5.3 serial i/o mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 d c 1 6 ] bn a m ef u n c t i o n s s e r i a l i / o m o d e r e g i s t e r 0 , 1i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 0 1 : f ( x i n ) / 1 6 1 0 : f ( x i n ) / 3 2 1 1 : f ( x i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 s e r i a l i / o p o r t s e l e c t i o n b i t ( s m 3 ) 6 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0 : p 4 0 , p 4 1 1 : s o u t ( / i n ) , s c l k 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : l s b f i r s t 1 : m s b f i r s t 4 f i x t h i s b i t t o 0 . 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . a f t e r r e s e t rw 0 0 0 0 0 0rw rw rw r w rw rw 0r s e r i a l i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n . 1 : i n p u t s i g n a l f r o m s o u t p i n . 0 30 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.5.1 serial i/o common transmission/recep- tion mode by writing 1 to bit 6 of the serial i/o mode register, signals s in and s out are switched internally to be able to transmit or receive the serial data. figure 8.5.4 shows signals on serial i/o common transmission/re- ception mode. note: when receiving the serial data after writing ff 16 to the serial i/o regis- ter. fig. 8.5.4 signals on serial i/o common transmission/reception mode s e r i a l i / o s h i f t r e g i s t e r ( 8 ) 1 0 c l o c k s c l k s o u t ( / i n ) s i n s m 6 s m : s e r i a l i / o m o d e r e g i s t e r 31 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 8.6.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency f : system clock = f(x in )/2 note : we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00da 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). 8.6 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 8.6.1 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8.6.1 shows multi-master i 2 c-bus interface func- tions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 8.6.1 block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register (s1) b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 i 2 c control register (s1d) bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circuit eso 2 2 32 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.1 i 2 c data shift register the i 2 c data shift register (s0 : address 00d7 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00da 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00d9 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. fig. 8.6.2 data shift register b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) [ a d d r e s s 0 0 d 7 1 6 ] b f u n c t i o n sa f t e r r e s e trw i c d a t a s h i f t r e g i s t e r 0 t o 7 t h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a . i n d e t e r m i n a t e 2 n o t e : 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n a m e d 0 t o d 7 rw 33 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.2 i 2 c address register the i 2 c address register (address 00d8 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. (1) bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. (2) bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. fig. 8.6.3 i 2 c address register b 7b 6b 5b 4b 3b 2b 1b 0 0 r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 d 8 1 6 ] b n a m e f u n c t i o n s 0 0 a f t e r r e s e t r w r r w 34 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.3 i 2 c clock control register the i 2 c clock control register (address 00db 16 ) is used to set ack control, scl mode and scl frequency. (1) bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. (2) bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. (3) bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgement fig. 8.6.4 i 2 c address register (4) bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s 0 0 d b 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 t o 4 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 t o c c r 4 ) 7 5 6 s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e 0 s t a n d a r d c l o c k m o d e b n a m e f u n c t i o n s a f t e r r e s e t r w 0 0 0 a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . 0 : n o a c k c l o c k 1 : a c k c l o c k h i g h s p e e d c l o c k m o d e s e t u p d i s a b l e d s e t u p d i s a b l e d 0 0 t o 0 2 s e t u p d i s a b l e d 3 3 3 0 3 s e t u p d i s a b l e d 2 5 0 0 4 1 0 0 4 0 0 ( s e e n o t e ) 0 5 8 3 . 31 6 6 0 6 5 0 0 / c c r v a l u e 1 0 0 0 / c c r v a l u e . . . 1 7 . 2 3 4 . 5 1 d 1 6 . 63 3 . 3 1 e 1 6 . 1 3 2 . 3 1 f ( a t f = 4 m h z , u n i t : k h z ) n o t e : a t 4 0 0 k h z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 3 : 2 i n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 1 : 1 s e t u p v a l u e o f c c r 4 C c c r 0 r w r w r w r w 35 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.4 i 2 c control register the i 2 c control register (address 00da 16 ) controls the data commu- nication format. (1) bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. (2) bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00d9 16 ). ? writing data to the i 2 c data shift register (address 00d7 16 ) is dis- abled. (3) bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to 8.6.5 i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. (4) bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00d8 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. (5) bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 8.6.5). fig. 8.6.5 connection port control by bsel0 and bsel1 note: set the corresponding direction register to 1 to use the port as multi-master i 2 c-bus interface. 0 1 b s e l 0 s c l 1 / p 1 1 s c l 2 / p 1 2 0 1 b s e l 1 0 1 b s e l 0 s d a 1 / p 1 3 s d a 2 / p 1 4 0 1 b s e l 1 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e s c l s d a 36 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.6.6 i 2 c control register b 7b 6b 5b 4b 3b 2b 1b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t 5a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s ( b s e l 0 , b s e l 1 ) b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 , s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s 0 0 d a 1 6 ] i 2 c c o n t r o l r e g i s t e r b n a m e f u n c t i o n s a f t e r r e s e t r w 2 r w r w r w r w r w 37 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.5 i 2 c status register the i 2 c status register (address 00d9 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). (2) bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition. ] general call: the master transmits the general call address 00 16 to all slaves. (3) bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. n in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start con- dition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00d8 16 ). ? a general call is received. n in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address regis- ter (8 bits consists of slave address and rbw), the first bytes match. n the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). (4) bit 3: arbitration lost ] detecting flag (al) n the master transmission mode, when a device other than the mi- crocomputer sets the sda to l,, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to 0. when arbitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ] arbitration lost: the status in which communication as a master is disabled. (5) bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 8.6.8 shows an interrupt request sig- nal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00d7 16 ). ? when the eso bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception (6) bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (see note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 c control register (address 00da 16 ) is 0 and at reset, the bb flag is kept in the 0 state. (7) bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00da 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 ___ (transmit) if the least significant bit (r/w bit) of the address data trans- ___ mitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset 38 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (8) bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when arbitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset fig. 8.6.7 i 2 c status register b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 d 9 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : s l a v e r e c i e v e m o d e 0 1 : s l a v e t r a n s m i t m o d e 1 0 : m a s t e r r e c i e v e m o d e 1 1 : m a s t e r t r a n s m i t m o d e 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b u s f r e e 1 : b u s b u s y b u s b u s y f l a g ( b b ) 0 : i n t e r r u p t r e q u e s t i s s u e d 1 : n o i n t e r r u p t r e q u e s t i s s u e d i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n o t d e t e c t e d 1 : d e t e c t e d a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : a d d r e s s m i s m a t c h 1 : a d d r e s s m a t c h s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o g e n e r a l c a l l d e t e c t e d 1 : g e n e r a l c a l l d e t e c t e d g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l a s t b i t = 0 1 : l a s t b i t = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) fig. 8.6.8 interrupt request signal generation timing s c l p i n i i c i r q note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output, when the following condition is satisfied: a start condition is set by another master device. 39 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.6 start condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) to set the mst, trx and bb bits to 1. a start condition will then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 8.6.9 for the start condition generation timing diagram, and table 8.6.2 for the start condition/ stop condition generation timing table. fig. 8.6.9 start condition generation timing diagram i 2 c status register write signal set time for bb flag hold time setup time scl sda bb flag setup time 8.6.7 stop condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition genera- tion timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 8.6.10 for the stop condition generation timing diagram, and table 8.6.2 for the start condition/stop condition generation timing table. fig. 8.6.10 stop condition generation timing diagram table 8.6.2 start condition/stop condition generation tim- ing table item setup time (start condition) setup time (stop condition) hold time set/reset time for bb flag standard clock mode 5.0 m s (20 cycles) 4.25 m s (17 cycles) 5.0 m s (20 cycles) 3.0 m s (12 cycles) high-speed clock mode 2.5 m s (10 cycles) 1.75 m s (7 cycles) 2.5 m s (10 cycles) 1.5 m s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l r e s e t t i m e f o r b b f l a g h o l d t i m e s e t u p t i m e s c l s d a b b f l a g 40 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.8 start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 8.6.11 and table 8.6.3. only when the 3 conditions of table 8.6.3 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq is generated to the cpu. fig. 8.6.11 start condition/stop condition detect timing dia- gram standard clock mode 6.5 m s (26 cycles) < scl release time 3.25 m s (13 cycles) < setup time 3.25 m s (13 cycles) < hold time high-speed clock mode 1.0 m s (4 cycles) < scl release time 0.5 m s (2 cycles) < setup time 0.5 m s (2 cycles) < hold time table 8.6.3 start condition/stop condition detect conditions note: absolute time at f = 4 mhz. the value in parentheses denotes the num- ber of f cycles. h o l d t i m e s e t u p t i m e s c l s d a ( s t a r t c o n d i t i o n ) s d a ( s t o p c o n d i t i o n ) s c l r e l e a s e t i m e h o l d t i m e s e t u p t i m e 8.6.9 address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. (1) 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00d8 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 8.6.12, (1) and (2). (2) 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 1. an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, an address com- parison between the rbw bit of the i 2 c address register (address 00d8 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00d9 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00d7 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00d8 16 ) to 1 by software. this processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00d8 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 8.6.12, (3) and (4). 41 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.6.10 example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00d8 16 ) and 0 in the rbw bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 00db 16 ). a set 10 16 in the i 2 c status register (address 00d9 16 ) and hold the scl at the high. set a communication enable status by setting 48 16 in the i 2 c control register (address 00da 16 ). ? set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00d7 16 ) and set 0 in the least significant bit. set f0 16 in the i 2 c status register (address 00d9 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. 2 set transmit data in the i 2 c data shift register (address 00d7 16 ). at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step ? . set d0 16 in the i 2 c status register (address 00d9 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. 8.6.11 example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00d8 16 ) and 0 in the rbw bit. set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 00db 16 ). a set 10 16 in the i 2 c status register (address 00d9 16 ) and hold the scl at the high. set a communication enable status by setting 48 16 in the i 2 c control register (address 00da 16 ). ? when a start condition is received, an address comparison is made. ?when all transmitted address are0 (general call): ad0 of the i 2 c status register (address 00d9 16 ) is set to 1and an interrupt request signal occurs. ?when the transmitted addresses match the address set in : ass of the i 2 c status register (address 00d9 16 ) is set to 1 and an interrupt request signal occurs. ?in the cases other than the above: ad0 and aas of the i 2 c status register (address 00d9 16 ) are set to 0 and no interrupt request signal occurs. 2 set dummy data in the i 2 c data shift register (address 00d7 16 ). ? when receiving control data of more than 1 byte, repeat step ? . when a stop condition is detected, the communication ends. 42 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.6.12 address data communication format ss l a v e a d d r e s s a d a t aa d a t aa / a p r / w 7 b i t s 0 ? t o 8 b i t s1 t o 8 b i t s ss l a v e a d d r e s s a d a t a ad a t a ap 7 b i t s 1 ? t o 8 b i t s1 t o 8 b i t s ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s 1 s t 7 b i t s a a d a t a 7 b i t s 0 ? b i t s1 t o 8 b i t s ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r s l a v e a d d r e s s 2 n d b y t e a d a t aa / a p 1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s a a 7 b i t s 0 ? b i t s7 b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e d a t a 1 t o 8 b i t s s r s l a v e a d d r e s s 1 s t 7 b i t s a d a t a a p 1 t o 8 b i t s 1 ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s:s t a r t c o n d i t i o np : s t o p c o n d i t i o n a:a c k b i tr / w : r e a d / w r i t e b i t s r:r e s t a r t c o n d i t i o n f r o m m a s t e r t o s l a v e f r o m s l a v e t o m a s t e r r / w r / w r / w r / w 8.6.12 precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the raead-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0) when executing the read-modify-write instruction for this register during transfer, data may become a value not intended. ?i 2 c address register (s0d) when the read-modify-write instruction is executed for this register at detecting the stop condition, data may become a value not ______ intended. it is because hardware changes the read/write bit (rbw) at the above timing. ?i 2 c status register (s1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ?i 2 c control register (s1d) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended. because hardware changes the bit counter (bc0Cbc2) at the above timing. ?i 2 c clock control register (s2) the read-modify-write instruction can be executed for this register. (2) start condition generating procedure us- ing multi-master procedure example (the necessary conditions of the generating procedure are described as the following to ? ). ? ? lda (taking out of slave address value) sei (interrupt disabled) bbs 5,s1,busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) ? ? busbusy: cli (interrupt enabled) ? ? use sta, stx or sty of the zero page addressing instruction for writing the slave address value to the i 2 c data shift register. a use ldm instruction for setting trigger of start condition gener- ating. write the slave address value of above and set trigger of start condition generating of above a continuously shown the above procedure example. ? disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. 43 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (3) restart condition generating procedure procedure example (the necessary conditions of the generating procedure are described as the following to ? .) execute the following procedure when the pin bit is 0. ? ? ldm #$00, s1 (select slave receive mode) lda (taking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of restart condition generating) cli (interrupt enabled) ? ? select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the sda pin is released. a the scl pin is released by writing the slave address value to the i 2 c data shift register. use sta, stx or sty of the zero page addressing instruction for writing. use ldm instruction for setting trigger of restart condition gen- erating. ? write the slave address value of above a and set trigger of re- start condition generating of above ? continuously shown the above procedure example. disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) stop condition generating procedure procedure example (the necessary conditions of the generating procedure are described as the following to ? .) ? ? sei (interrupt disabled) ldm #$c0, s1 (select master transmit mode) nop (set nop) ldm #$d0, s1 (trigger of stop condition generating) cli (interrupt enabled) ? ? write 0 to the pin bit when master transmit mode is select. a execute nop instruction after setting of master transmit mode. also, set trigger of stop condition generating within 10 cycles af- ter selecting of master trasmit mode. disable interrupts during the following two process steps: ? select of master transmit mode ? trigger of stop condition generating (5) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simultaneously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not ex- ecute an instruction to set the mst and trx bits to 0 from 1 si- multaneously when the pin bit is 1. it is because it may become the same as above. (6) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. 44 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.7 pwm output function this microcomputer is equipped with two 14-bit pwm (da) and eight 8-bit pwms (pwm0Cpwm7). da1 and da2 have a 14-bit resolution with the minimum resolution bit width of 0.25 m s and a repeat period of 4096 m s (for f(x in ) = 8 mhz). pwm0Cpwm7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 m s and repeat period of 1024 m s (for f(x in ) = 8 mhz). figure 8.7.1 shows the pwm block diagram. the pwm timing gen- erating circuit applies individual control signals to da and pwm0C pwm7 using f(x in ) divided by 2 as a reference signal. 8.7.1 data setting when outputting da, first set the high-order 8 bits to the da-h regis- ter (address 00ce 16 ), then the low-order 6 bits to the da-l register (address 00cf 16 ). when outputting pwm0Cpwm7, set 8-bit output data to the pwmi register (i means 0 to 7; addresses 00d0 16 to 00d4 16 , 00f6 16 to 00f8 16 ). 8.7.2 transferring data from registers to pwm circuit data transfer from the 8-bit pwm register to the 8-bit pwm circuit is executed at writing data to the register. the signal output from the 8-bit pwm output pin corresponds to the contents of this register. also, data transfer from the da register (addresses 00ce 16 and 00cf 16 ) to the 14-bit pwm circuit is executed at writing data to the da-l register (address 00cf 16 ). reading from the da-h register (address 00ce 16 ) means reading this transferred data. accordingly, it is possible to confirm the data being output from the da output pin by reading the da register. 8.7.3 operating of 8-bit pwm the following explains pwm operation. first, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automatically), so that the pwm count source is supplied. pwm0Cpwm3 are also used as pins p6 0 Cp6 3 , pwm4Cpwm7 are also used as ports p0 0 Cp0 3 , respectively. for pwm0Cpwm3, set the corresponding bits of the ports p6 direction register to 1 (output mode). for pwm4Cpwm7, set those of the port p0 direction regis- ter to 1. and select each output polarity by bit 3 of pwm output control register 2 (address 00d6 16 ). then, for pwm0Cpwm5, set bits 2 to 7 of pwm output control register 1 to 1 (pwm output). for pwm6 and pwm7, set bits 0 and 1 of pwm output control register 2 to 1. the pwm waveform is output from the pwm output pins by setting these registers. figure 8.7.2 shows the 8-bit pwm timing. one cycle (t) is com- posed of 256 (2 8 ) segments. the 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 8.7.2 (a). the 8-bit pwm outputs waveform which is the logical sum (or) of pulses corresponding to the con- tents of bits 0 to 7 of the 8-bit pwm register. several examples are shown in figure 8.7.2 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm regis- ter. a length of entirely high output cannot be output, i.e. 256/256. 8.7.4 operating of 14-bit pwm as with 8-bit pwm, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automati- cally), so that the pwm count source is supplied. next, select the output polarity by bit 2 of pwm output control register 2 (address 00d6 16 ). then, the 14-bit pwm outputs from the da output pin by setting bit 1 of pwm output control register 1 to 0 (at reset, this bit already set to 0 automatically) to select the da output. the output example of the 14-bit pwm is shown in figure 8.7.3. the 14-bit pwm divides the data of the da latch into the low-order 6 bits and the high-order 8 bits. the fundamental waveform is determined with the high-order 8-bit data d h . a high area with a length t 5 d h (high area of funda- mental waveform) is output every short area of t = 256 t = 64 m s ( t is the minimum resolution bit width of 250 ns). the high level area increase interval (t m ) is determined with the low-order 6-bit data d l . the high are of smaller intervals t m shown in table 5 is longer by t than that of other smaller intervals in pwm repeat period t = 64t. thus, a rectangular waveform with the different high width is output from the da pins. accordingly, the pwm output changes by t unit pulse width by changing the contents of the da-h and da-l registers. a length of entirely high cannot be output, i. e. 256/256. 8.7.5 output after reset at reset, the output of ports p6 0 Cp6 3 and p0 0 Cp0 3 are in the high- impedance state, and the contents of the pwm register and the pwm circuit are undefined. note that after reset, the pwm output is undefined until setting the pwm register. lsb table 8.7.1 relation between the low-order 6-bit data and high- level area increase interval area longer by t than that of other t m (m = 0 to 63) nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63 low-order 6 bits of data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 45 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.7.1 pwm block diagram pwm1 register (address : 00d1 16 ) 1/2 x in pwm timing generating circuit pwm register ( address : 00d0 16 ) b7 b0 8 8-bit pwm circuit pn3 p6 0 pw2 d6 0 pwm0 p6 1 pw3 d6 1 pwm1 p6 2 pw4 d6 2 pwm2 p6 3 pw5 d6 3 pwm3 p0 0 pw6 d0 0 pwm4 p0 2 pw7 d0 2 pwm5 pwm2 register (address : 00d2 16 ) pwm3 register (address : 00d3 16 ) pwm4 register (address : 00d4 16 ) pwm5 register (address : 00f6 16 ) pw0 is as same contents pwm6 register (address : 00d7 16 ) pwm7 register (address : 00f8 16 ) p0 3 pn1 d0 3 pwm7 p0 2 pn0 d0 2 pwm6 inside of with the others. data bus selection gate : pw f pwm output control register 1 pn f pwm output control register 2 connected to black colored side when reset. pass gate d0 f port p0 direction register 14-bit pwm circuit pn2 pn4 pw1 da msb da-h register (address : 00ce 16 ) da latch (14 bits) da-l register (see note) (address : 00cf 16 ) lsb 8 6 14 6 da b7 b0 note: the da-l register also functions as the low-order 6 bits of the da latch. d6 f port p6 direction register 46 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.7.2 pwm timing ( a ) p u l s e s s h o w i n g t h e w e i g h t o f e a c h b i t 1 3 5 7 9 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 5 5 4 1 2 2 0 2 8 3 6 4 4 5 2 6 0 6 8 7 6 8 4 9 2 1 0 0 1 0 8 1 1 6 1 2 4 1 3 2 1 4 0 1 4 8 1 5 6 1 6 4 1 7 2 1 8 0 1 8 8 1 9 6 2 0 4 2 1 2 2 2 0 2 2 8 2 3 6 2 4 4 2 5 2 8 1 6 4 8 8 0 1 1 2 1 4 4 1 7 6 2 0 8 2 4 0 2 4 4 0 5 6 7 2 8 8 1 0 4 1 2 0 1 3 6 1 5 2 1 6 8 1 8 4 2 0 0 2 1 6 2 3 2 2 4 8 3 2 9 6 1 6 0 2 2 4 6 4 1 9 2 b i t 7 2 6 1 0 1 4 1 8 2 2 2 6 3 0 3 4 3 8 4 2 4 6 5 0 5 4 5 8 6 2 6 6 7 0 7 4 7 8 8 2 8 6 9 0 9 4 9 8 1 0 2 1 0 6 1 1 0 1 1 4 1 1 8 1 2 2 1 2 6 1 3 0 1 3 4 1 3 8 1 4 2 1 4 6 1 5 0 1 5 4 1 5 8 1 6 2 1 6 6 1 7 0 1 7 4 1 7 8 1 8 2 1 8 6 1 9 0 1 9 4 1 9 8 2 0 2 2 0 6 2 1 0 2 1 4 2 1 8 2 2 2 2 2 6 2 3 0 2 3 4 2 3 8 2 4 2 2 4 6 2 5 0 2 5 4 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 1 2 8 b i t 0 p w m o u t p u t t = 4 m s t = 1 0 2 4 m s f ( x i n ) = 8 m h z ( b ) e x a m p l e o f 8 - b i t p w m t 0 0 1 6 ( 0 ) 0 1 1 6 ( 1 ) 1 8 1 6 ( 2 4 ) f f 1 6 ( 2 5 5 ) t = 2 5 6 t 47 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.7.3 14-bit pwm timing (f(x in ) = 8 mhz) 0 . 2 5 m s b 7b 0 b 6b 5b 4b 3b 2b 1 0 0 010110 b 1 3b 6 00 010110 b 0 b 5 101000 s e t 2 c 1 6 t o d a - h r e g i s t e r . [ d a - h r e g i s t e r ] d h a t w r i t i n g o f d a - l b 0 b 6b 5b 4b 3b 2b 1 0 10100 s e t 2 8 1 6 t o d a - l r e g i s t e r . [ d a - l r e g i s t e r ] d l a t w r i t i n g o f d a - l t h e s e b i t s d e c i d e h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m . t h e s e b i t s d e c i d e s m a l l e r i n t e r v a l t m i n w h i c h h i g h l e v a l a r e a i s [ h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m + t ] . m i n i m u m r e s o l u t i o n b i t w i d t h 0 . 2 5 m s h i g h - o r d e r 8 - b i t v a l u e o f d a l a t c h 5 h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m f f0 0 d 3 f ef d d 6d 40 20 1 d 5 1 4 - b i t p w m o u t p u t 8 - b i t c o u n t e r 0 . 2 5 m s 5 4 4 f f0 0 d 3 f ef dd 6d 40 20 1 d 5 1 4 - b i t p w m o u t p u t 8 - b i t c o u n t e r 0 . 2 5 m s 5 4 5 f u n d a m e n t a l w a v e f o r m w a v e f o r m o f s m a l l e r i n t e r v a l t m s p e c i f i e d b y l o w - o r d e r 6 b i t s f u n d a m e n t a l w a v e f o r m o f s m a l l e r i n t e r v a l t m w h i c h i s n o t s p e c i f i e d b y l o w - o r d e r 6 b i t s i s n o t c h a n g e d . 1 4 - b i t p w m o u t p u t l o w - o r d e r 6 - b i t o u t p u t o f d a l a t c h 0 . 2 5 m s 5 4 4 t = 0 . 2 5 m s t = 4 0 9 6 m s @ r e p e a t p e r i o d t 0 t 1 t 2 t 3 t 4 t 5 t 5 9 t 6 0 t 6 1 t 6 2 t 6 3 [ d a l a t c h ] b 7 2 c 2 b 2 a 0 3 0 2 0 10 02 c 2 b 2 a 0 3 0 2 0 10 0 48 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.7.4 pwm output control register 1 fig. 8.7.5 pwm output control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) [ a d d r e s s 0 0 d 5 b a f t e r r e s e t rw p w m o u t p u t c o n t r o l r e g i s t e r 1 0 1 2 3 4 0 n a m ef u n c t i o n s d a , p w m c o u n t s o u r c e s e l e c t i o n b i t ( p w 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p p 6 0 / p w m 0 o u t p u t s e l e c t i o n b i t ( p w 2 ) 0 : p 6 0 o u t p u t 1 : p w m 0 o u t p u t p 6 1 / p w m 1 o u t p u t s e l e c t i o n b i t ( p w 3 ) 0 : p 6 1 o u t p u t 1 : p w m 1 o u t p u t p 6 2 / p w m 2 o u t p u t s e l e c t i o n b i t ( p w 4 ) 0 : p 6 2 o u t p u t 1 : p w m 2 o u t p u t 5 p 6 3 / p w m 3 o u t p u t s e l e c t i o n b i t ( p w 5 ) 0 : p 6 3 o u t p u t 1 : p w m 3 o u t p u t 6 p 0 0 / p w m 4 o u t p u t s e l e c t i o n b i t ( p w 6 ) 0 : p 0 0 o u t p u t 1 : p w m 4 o u t p u t d a / p n 4 s e l e c t i o n b i t ( p w 1 ) 0 : d a o u t p u t 1 : p n 4 o u t p u t 7 p 0 1 / p w m 5 o u t p u t s e l e c t i o n b i t ( p w 7 ) 0 : p 0 1 o u t p u t 1 : p w m 5 o u t p u t 0 0 0 0 0 0 0 1 6 ] rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 2 (pn) [address 00d6 16 ] b after reset rw pwm output control register 2 0 2 3 4 0 name functions da output polarity selection bit (pn2) 0 : positive polarity 1 : negative polarity pwm output polarity selection bit (pn3) da general-purpose output bit (pn4) 0 : output low 1 : output high 5 to 7 0 0 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?.? 0 : positive polarity 1 : negative polarity rw rw rw rw r p0 2 /pwm6 output selection bit (pn0) 0 : p0 2 1 : pwm6 output 1 0rw p0 3 /pwm7 output selection bit (pn1) 0 : p0 3 1 : pwm7 output 49 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.8 a-d comparator a-d comparator consists of 6-bit d-a converter and comparator. a-d comparator block diagram is shown in figure 8.8.1. the reference voltage v ref for d-a conversion is set by bits 0 to 5 of the a-d control register (address 00ef 16 ). the comparison result of the analog input voltage and the reference voltage v ref is stored in bit 4 of the a-d mode register (address 00ee 16 ). for a-d comparison, set 0 to corresponding bits of the direction register to use ports as analog input pins. write the data for select of analog input pins to bits 0 to 2 of the a-d control register 1 and write the digital value corresponding to v ref to be compared to the bits 0 to 5 of the a-d control register. the voltage comparison starts by writing to the a-d control register 2, and it is completed after 16 ma- chine cycles (nop instruction 5 8). fig. 8.8.1 a-d comparator block diagram a - d m o d e r e g i s t e r b i t s 0 t o 2 c o m p a r a t o r c o n t r o l d a t a b u s b i t 4 s w i t c h t r e e a - d c o n t r o l r e g i s t e r r e s i s t o r l a d d e r c o m p a - r a t o r a n a l o g s i g n a l s w i t c h b i t 5b i t 4b i t 3b i t 2b i t 1 b i t 0 a - d m o d e r e g i s t e r a - d 1 a - d 2 a - d 3 a - d 4 a - d 5 a - d 6 a - d 7 a - d 8 50 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.8.2 a-d mode register b 7b 6b 5b 4b 3b 2b 1b 0 a - d m o d e r e g i s t e r ( a d m ) [ a d d r e s s 0 0 e e 1 6 ] b a f t e r r e s e t rw a - d m o d e r e g i s t e r 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d m 0 t o a d m 2 ) n a m ef u n c t i o n s b 2 b 1 b 0 0 0 0 : a - d 1 0 0 1 : a - d 2 0 1 0 : a - d 3 0 1 1 : a - d 4 1 0 0 : a - d 5 1 0 1 : a - d 6 1 1 0 : a - d 7 1 1 1 : a - d 8 4 s t o r a g e b i t o f c o m p a r i s o n r e s u l t ( a d m 4 ) 0 : i n p u t v o l t a g e < r e f e r e n c e v o l t a g e 1 : i n p u t v o l t a g e > r e f e r e n c e v o l t a g e 0 i n d e t e r m i n a t e 0 3t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . rw r r 0 5 t o 7 n o t h i n g i s a s s i g n e d . t h i s b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r fig. 8.8.3 a-d control register b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n t r o l r e g i s t e r ( a d c ) [ a d d r e s s 0 0 e f 1 6 ] b a f t e r r e s e t r w a - d c o n t r o l r e g i s t e r 0 t o 5 6 , 7 0 0 n a m ef u n c t i o n s d - a c o n v e r t e r s e t b i t s ( a d c 0 t o a d c 5 ) b 0 b 1 b 2 b 3 b 4 b 5 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e e d o u t , t h e v a l u e s a r e 0 . 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3 / 1 2 8 v c c : 5 / 1 2 8 v c c : 1 2 3 / 1 2 8 v c c : 1 2 5 / 1 2 8 v c c : 1 2 7 / 1 2 8 v c c : 1 / 1 2 8 v c c r w r 51 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.9.2 rom correction enable register fig. 8.9.1 rom correction address registers 8.9 rom correction function this can correct program data in rom. up to 2 addresses can be corrected, a program for correction is stored in the rom correction memory in ram as the top address. the rom correction vectors are 2 vectors. vector 1 : address 02c0 16 vector 2 : address 02e0 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the rom correction vector as the top address, the main program branches to the correction program stored in the rom memory for correction. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. the rom correction function is controlled by the rom correction enable register. notes 1: specify the first address (op code address) of each instruction as the rom correction address. 2: use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3: do not set the same rom correction address to vectors 1 and 2. 4: only m37212m8-xxxsp and m37212efsp/fp have rom correc- tion function. 0 2 1 7 1 6 r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) 0 2 1 8 1 6 r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) 0 2 1 9 1 6 r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) 0 2 1 a 1 6 r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) b 7b 6b 5b 4b 3b 2b 1b 0 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) [ a d d r e s s 0 2 1 b 1 6 ] ba f t e r r e s e t r o m c o r r e c t i o n e n a b l e r e g i s t e r 0 v e c t o r 1 e n a b l e b i t ( r c 0 ) n a m ef u n c t i o n s 0 : d i s a b l e d 1 : e n a b l e d 1 v e c t o r 2 e n a b l e b i t ( r c 1 ) 0 : d i s a b l e d 1 : e n a b l e d 4 t o 7 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 0 0 0 0 2 , 3 f i x t h e s e b i t s t o 0 . 0 rw rw rw r rw 52 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10 osd functions table 8.10.1 outlines the osd functions. this microcomputer incor- porates an osd control circuit of 24 characters 5 2 lines. osd is controlled by the crt control register. up to 256 kinds of characters can be displayed. the colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. a combina- tion of up to 8 colors can be obtained by using each output signal (r, g, and b). characters are displayed in a 12 5 16 dots configuration to obtain smooth character patterns (refer to figure 8.10.1). the following shows the procedure how to display characters on the crt screen. write the display character code in osd ram. specify the display color by using the color register. a write the color register in which the display color is set in osd ram. specify the vertical position by using the vertical position register. ? specify the character size by using the character size register. specify the horizontal position by using the horizontal position register. 2 write the display enable bit to the designated block display flag of the crt control register. when this is done, the osd starts ac- cording to the input of the v sync signal. table 8.10.1 features of each display mode number of display characters 24 characters 5 2 lines dot structure 12 5 16 dots kinds of characters 256 kinds kinds of character sizes 3 kinds attribute border (black) character font coloring 1 screen : 8 kinds (per character unit) character background coloring 1 screen : 8 kinds (per character unit) osd output r, g, b display position horizontal: 64 levels, vertical: 128 levels display expansion (multiline display) possible parameter functions 53 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 the osd circuit has an extended display mode. this mode allows multiple lines (3 lines or more) to be displayed on the screen by inter- rupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. figure 8.10.1 shows the configuration of osd character. figure 8.10.2 shows the block diagram of the osd circuit. figure 8.10.3 shows the crt control register. fig. 8.10.1 configuration of osd character display area 12 dot s 16 dot s 54 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.10.2 block diagram of osd circuit d i s p l a y o s c i l l a t i o n c i r c u i t o s c 1 o s c 2 h s y n c v s y n c o s d r a m 1 0 b i t s ~ 2 4 c h a r a c t e r s ~ 2 l i n e s d a t a b u s o s d r o m 1 2 d o t s ~ 1 6 d o t s ~ 2 5 6 c h a r a c t e r s s h i f t r e g i s t e r 1 2 - b i t c l o c k f o r o s d o u t p u t c i r c u i t r g b o s d c o n t r o l c i r c u i t o u t 1 o u t 2 c o n t r o l r e g i s t e r s f o r o s d ( a d d r e s s 0 0 e 0 1 6 ) ( a d d r e s s e s 0 0 e 1 1 6 , 0 0 e 2 1 6 ) ( a d d r e s s e s 0 0 e 4 1 6 ) ( a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 ) ( a d d r e s s 0 0 e a 1 6 ) ( a d d r e s s 0 0 e c 1 6 ) h o r i z o n t a l p o s i t i o n r e g i s t e r v e r t i c a l p o s i t i o n r e g i s t e r c h a r a c t e r s i z e r e g i s t e r c o l o r r e g i s t e r c r t c o n t r o l r e g i s t e r c r t p o r t c o n t r o l r e g i s t e r s h i f t r e g i s t e r 1 2 - b i t 55 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.10.3 crt control register b7 b6 b5 b4 b3 b2 b1 b0 crt control register (cc) [address 00ea 16 ] b name functions after reset r w crt control register 0 all-blocks display control bit (cc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 6 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. block 2 display control bit (cc2) rw rw rw r 7 0 : p1 0 1 : out2 0 p1 0 /out2 pin switch bit (cc7) rw 56 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.1 display position the display positions of characters are specified in units called a block. there are 2 blocks, blocks 1 and 2. up to 24 characters can be displayed in each block (refer to 8.10.3 memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display start position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4t c (t c = osd oscillation cycle). the display start position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. blocks are displayed in conformance with the following rules: ? block 2 is displayed after the display of block 1 is completed (figure 8.10.4 (a)). ? when the display position of block 1 is overlapped with that of block 2 (figure 8.10.4 (b)), the block 1 is displayed on the front. ? when another block display position appears while one block is displayed (figure 8.10.4 (c)),only block 1 is displayed. similarly, when multiline display, block 1 is displayed after the display of block 2 is completed. fig. 8.10.4 display position h r c v2 b l o c k 1 b l o c k 2 ( a ) e x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d b l o c k 1 ( b ) e x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 ( b l o c k 2 i s n o t d i s p l a y e d ) h r c v1 c v2 ( c ) e x a m p l e w h e n b l o c k 2 o v e r l a p s i n p r o c e s s o f b l o c k 1 b l o c k 2 n o t e s 1 : c v 1 o r c v 2 i n d i c a t e s t h e v e r t i c a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k 1 o r 2 . 2 : h r i n d i c a t e s t h e h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k 1 o r 2 . c v1 h r c v 1 = c v 2 c v1 b l o c k 1 ( s e c o n d ) ? n o t d i s p l a y e d ? n o t d i s p l a y e d b l o c k 1 57 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 the vertical display start position is determined by counting the hori- zontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the crt port control register (address 00ec 16 ). fig. 8.10.5 supplement explanation for display position w h e n b i t s 0 a n d 1 o f t h e c r t p o r t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 e c 1 6 ) a r e s e t t o 1 ( n e g a t i v e p o l a r i t y ) v s y n c s i g n a l i n p u t v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r 0 . 2 5 t o 0 . 5 0 [ m s ] ( a t f ( x i n ) = 8 m h z ) p e r i o d o f c o u n t i n g h s y n c s i g n a l ( s e e n o t e 2 ) h s y n c s i g n a l i n p u t n o t c o u n t 12345 n o t e s 1 : t h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f h s y n c s i g n a l a f t e r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r . 2 : d o n o t g e n e r a t e f a l l i n g e d g e o f h s y n c s i g n a l n e a r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r . 3 : t h e p u l s e w i d t h o f v s y n c a n d h s y n c n e e d s 8 m a c h i n e c y c l e s o r m o r e . 8 m a c h i n e c y c l e s o r m o r e 8 m a c h i n e c y c l e s o r m o r e 58 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.10.6 vertical position register i the vertical display start position for each block can be set in 512 steps (where each step is 1t h (t h : h sync cycle)) as values 00 16 to 7f 16 in vertical position register i (i = 1 and 2) (addresses 00e1 16 and 00e2 16 ) the vertical position register i is shown in figure 8.10.6. b7 b6 b5 b4 b3 b2 b1 b0 vertical position register i (cvi) (i = 1 and 2) [addresses 00e1 16, 00e2 16 ] b name functions after reset r w vertical position register i 0 to 6 7 vertical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cvi : cvi0 to cvi6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. rw r 59 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 the horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4t c , t c being the osd oscillation cycle) as values 00 16 to 3f 16 in bits 0 to 5 of the horizontal posi- tion register (address 00d1 16 ). the horizontal position register is shown in figure 8.10.7. fig. 8.10.7 horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6, 7 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0 nothing is assigned. these bits are write disable bits. when thses bits are read out, the values are ?. rw r 60 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.10.8 character size register 8.10.2 character size the size of characters to be displayed can be from 3 sizes for each block. use the character size register (address 00e4 16 ) to set a char- acter size. the character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. figure 8.10.8 shows the character size register. the character size can be selected from 3 sizes: minimum size, me- dium size and large size. each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (t c ) in the width (horizontal) direction. the minimum size consists of [1 scanning line] 5 [1t c ]; the medium size consists of [2 scanning lines] 5 [2t c ]; and the large size con- sists of [3 scanning lines] 5 [3t c ]. table 8.10.2 shows the relation between the set values in the character size register and the charac- ter sizes. b7 b6 b5 b4 b3 b2 b1 b0 character size register (cs) [address 00e4 16 ] b name functions after reset r w character size register 0, 1 character size of block 1 selection bits (cs10, cs11) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. indeterminate 2,3 4 to 7 0 character size of block 2 selection bits (cs20,cs21) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. indeterminate rw rw r 61 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 mini- mum medium large horizontal display start position fig. 8.10.9 display start position of each character size (horizontal direction) note: the display start position in the horizontal direction is not affected by the character size. in other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to figure 8.10.9). set values of character size register width (horizontal) direction t c : oscillating cycle for display 1 t c 2 t c 3 t c height (vertical) direction scanning lines 1 2 3 character size minimum medium large this is not available csn1 0 0 1 1 csn0 0 1 0 1 table. 8.10.2 relation between set values in character size register and character sizes 62 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.3 clock for osd as a clock for display to be used for osd, it is possible to select one of the following 4 types. ? main clock supplied from x in pin ? main clock supplied from x in pin divided by i.5 ? clock from the ceramic resonator or the lc or oscillator from the pins osc1 and osc2 ? clock from the ceramic resonator or the quartz-crystal oscillator supplied from the pins osc1 and osc2. this osd clock for each block can be selected by the crt clock selection register (address 00ed 16 ). when selecting the main clock, set the oscillation frequency to 8 mhz. fig. 8.10.10 block diagram of osd selection circuit b 7b 6b 5b 4b 3b 2b 1b 0 c r t c l o c k s e l e c t i o n r e g i s t e r ( c k ) [ a d d r e s s 0 0 e d 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e t r w c r t c l o c k s e l e c t i o n r e g i s t e r 0 , 1 c r t c l o c k s e l e c t i o n b i t s ( c k 0 , c k 1 ) 0 s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r d i s p l a y , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n t a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 6 a n d p 3 7 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . a c e r a m i c r e s o n a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r ( s e e n o t e ) 2 t o 7 0 0 0 0 0 0 0 b 1 t h e c l o c k f o r d i s p l a y i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . f u n c t i o n s 00 b 0 o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) / 1 . 5 n o t e : i t i s n e c e s s a r y t o c o n n e c t o t h e r c e r a m i c r e s o n a t o r o r q u a r t z - c r y s t a l o s c i l l a t o r a c r o s s t h e p i n s x 0 0 1 1 11 f i x t h e s e b i t s t o 0 . i n a n d x o u t . r w r w 63 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.4 memory for osd there are 2 types of memory for osd : osd rom (addresses 10000 16 to 11fff 16 ) used to store character dot data and osd ram (addresses 0600 16 to 06b7 16 ) used to specify the characters and colors to be displayed. fig. 8.10.11 character font data storing address (1) osd rom (addresses 10000 16 to 11fff 16 ) the dot pattern data for osd characters is stored in osd rom. to specify the kinds of the character font, it is necessary to write the character code (table 8.10.3) into the osd ram. the osd rom has a capacity of 8k bytes. since 32 bytes are re- quired for 1 character data, the rom can stores up to 256 kinds of characters. the osd rom space is broadly divided into 2 areas. the [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display characters are stored in addresses 10000 16 to 107ff 16 and 11000 16 to 117ff 16 ; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 10800 16 to 10fff 16 and 11800 16 to 11fff 16 (refer to figure 8.10.11). note however that the high- order 4 bits in the data to be written to addresses 10800 16 to 10fff 16 and 11800 16 to 11fff 16 must be set to 1 (by writing data fx 16 ). data of the character font is specified shown in figure 8.10.11. 10xx0 16 +800 16 or 11xx0 16 +800 16 00 000000 00 000000 00 000010 00 000101 01 001000 01 001000 01 001000 00 010000 0 1 01 1111 001 00 100000 00 100000 00 100000 00 000000 00 000101 00 000010 0 1111 000 0 000 0 000 0 000 0 000 0 000 0 000 0 100 0 100 0 100 0 010 0 010 0 010 0 000 0 000 0 000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 0 0000 10xxf 16 +800 16 or 11xxf 16 +800 16 10xx0 16 or 11xx0 16 10xxf 16 or 11xxf 16 64 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 block block 1 block 2 display position (from left) 1st character 2nd character 3rd character : 22nd character 23rd character 24th character not used 1st character 2nd character 3rd character : 22nd character 23rd character 24th character character code specification 0600 16 0601 16 0602 16 : 0615 16 0616 16 0617 16 0618 16 : 061f 16 0620 16 0621 16 0622 16 : 0635 16 0636 16 0637 16 color specification 0680 16 0681 16 0682 16 : 0695 16 0696 16 0697 16 0698 16 : 069f 16 06a0 16 06a1 16 06a2 16 : 06b5 16 06b6 16 06b7 16 table 8.10.3 character code list (partially abbreviated) (2) osd ram (addresses 0600 16 to 06b7 16 ) the osd ram is allocated at addresses 0600 16 to 06b7 16 , and is divided into a display character code specification part, and color code specification part for each block. table 8.10.4 shows the con- tents of the osd ram. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0600 16 , write the color code at 0680 16 . the structure of the osd ram is shown in figure 8.10.12. table 8.10.4 contents of osd ram character code 00 16 character data storage address left 8 dots lines right 4 dots lines 10000 16 1000f 16 10800 16 1080f 16 01 16 10010 16 1001f 16 10810 16 1081f 16 02 16 10020 16 1002f 16 10820 16 1082f 16 03 16 10030 16 1003f 16 10830 16 1083f 16 : :: 7e 16 107e0 16 107ef 16 10fe0 16 10fef 16 7f 16 107f0 16 107ff 16 10ff0 16 10fff 16 80 16 11000 16 1100f 16 11800 16 1180f 16 81 16 11010 16 1101f 16 11810 16 1181f 16 : :: fd 16 117d0 16 117df 16 11fd0 16 11fdf 16 fe 16 117e0 16 117ef 16 11fe0 16 11fef 16 ff 16 117f0 16 117ff 16 to 11ff0 16 11fff 16 to to to to to to to to to to to to to to to to to to to to to 65 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.10.12 bit structure of osd ram [color specification] 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification 0 1 block 1 [character specification] specify 256 characters (?0 16 ?to ?f 16 ? character code 70 block 2 [character specification] 1st character : 0620 16 24th character : 0637 16 1st character : 0680 16 24th character : 0697 16 1st character : 0600 16 24th character : 0617 16 70 [color specification] 1st character : 06a0 16 24th character : 06b7 16 0 1 to to to to specify 256 characters (?0 16 ?to ?f 16 ? character code 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification 66 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.5 color register the color of a displayed character can be specified by setting the color to one of the 4 registers (co0 to co3: addresses 00e6 16 to 00e9 16 ) and then specifying that color register with the osd ram. there are 3 color outputs; r, g and b. by using a combination of these outputs, it is possible to set 8 colors. however, since only 4 color registers are available, up to 4 colors can be disabled at one time. r, g and b outputs are set by using bits 1 to 3 in the color register. bit 5 is used to specify whether a character output or blank output. bits 4, 6 and 7 are used to specify character background color. figure 8.10.12 shows the color register. fig. 8.10.13 color register i b 7b 6b 5b 4b 3b 2b 1b 0 c o l o r r e g i s t e r i ( c o i ) ( i = 0 t o 3 ) [ a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e t r w c o l o r r e g i s t e r i 0 0 r 1 g s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 2 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t i n d e t e r m i n a t e r w 2 r s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 3 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t r w 3 b s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 4 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 4 o u t 1 s i g n a l o u t p u t c o n t r o l b i t ( c o i 5 ) ( s e e n o t e s 1 , 2 ) 0 : c h a r a c t e r i s o u t p u t 1 : b l a n k i s o u t p u t r w 5 g s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 6 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 6 r s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 7 ) ( s e e n o t e 2 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 7 r w @ b s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 1 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . n o t e s 1 : w h e n b i t 5 = 0 a n d b i t 4 = 1 , t h e r e i s o u t p u t s a m e a s a c h a r a c t e r o r b o r d e r o u t p u t f r o m p i n o u t 1 . d o n o t s e t b i t 5 = 0 a n d b i t 4 = 0 . 2 : w h e n o n l y b i t 7 = 1 a n d b i t 5 0 , t h e r e i s o u t p u t f r o m p i n o u t 2 . i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e 67 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 table 8.10.5 display example of character background coloring (when green is set for a character and blue is set for backgroun d color) border selection register color register i coi7 coi6 coi5 coi4 coi3 coi2 coi1 md 0 g output b output out1 output character output out2 output 0 5 0 0 1 0 no output same output as character a green video signal and character color (green) are not mixed. no output (see note 2) 0 0 5 0 0 1 0 no output same output as character a video signal and character color (green) are not mixed. blank output 1 green no output tv image of character background is not displayed. blank output green no output (see note 2) 1 5 0 1 0 1 0 no output border output (black) video signal and character color (green) are not mixed. green no output (see note 2) 010010 00 1 tv image of character background is not displayed. blank output green 01010 00 no output (see note 2) background color blue 5 10 tv image of character background is not displayed. green 1 010 blank output 00 no output (see note 2) black no output 11 green no output (see note 2) 1 010 tv image of character background is not displayed. blank output 00 border output (black) background color ?border blue notes 1 : when coi5 = ??and coi4 = ?,?there is output same as a character or border output from the out1 pin. do not set coi5 = ??and coi4 = ?. 2 : when only coi7 = ??and coi5 = ?,?there is output from pin out2. 3 : the portion ??in which character dots are displayed is not mixed with any tv video signal. 4 : the wavy-lined arrows in the table denote video signals. 5 : n : 0 to 3, 5 : 0 or 1 border output (black) 1 (note 1) 1 68 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.6 border an border of 1 clock (1 dot) equivalent size can be added to a char- acter to be displayed in both horizontal and vertical directions. the border is output from the out pin. in this case, set bit 5 of a color register to 0 (character is output). border can be specified in units of block by using the border selec- tion register (address 00e5 16 ). figure 8.10.14 shows the border se- lection register. table 8.10.6 shows the relationship between the val- ues set in the border selection register and the character border func- tion. fig. 8.10.14 border selection register table 8.10.6 relationship between set value in border selection register and character border function b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out1 output border selection bit (md10) 0 : same output as r, g, b is output 1 : border output indeterminate 2 block 2 out1 output border selection bit (md20) 0 : same output as r, g, b is output 1 : border output indeterminate rw rw 0 3 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?.? r 0 1 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?.? r r, g, b output out1 output r, g, b output out1 output functions ordinary border including character example of output mdn0 0 1 border selection register fig. 8.10.15 example of border 69 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.7 multiline display this microcomputer can ordinarily display 2 lines on the crt screen by displaying 2 blocks at different vertical positions. in addition, it can display up to 16 lines by using osd interrupts. an osd interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. note: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the crt control register (address 00ea 16 ), an osd inter- rupt request does not occur (refer to figure 8.10.16). fig. 8.10.16 note on occurence of osd interrupt b l o c k 1 ( o n d i s p l a y ) b l o c k 2 ( o n d i s p l a y ) b l o c k 1 ( o n d i s p l a y ) b l o c k 2 ( o n d i s p l a y ) b l o c k 1 ( o n d i s p l a y ) b l o c k 2 ( o n d i s p l a y ) b l o c k 1 ( o f f d i s p l a y ) b l o c k 2 ( o f f d i s p l a y ) o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t n o o s d i n t e r r u p t r e q u e s t o n d i s p l a y ( o s d i n t e r r u p t r e q u e s t o c c u r s a t t h e e n d o f b l o c k d i s p l a y ) o f f d i s p l a y ( o s d i n t e r r u p t r e q u e s t d o e s n o t o c c u r a t t h e e n d o f b l o c k d i s p l a y ) n o o s d i n t e r r u p t r e q u e s t 70 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.8 osd output pin control the osd output pins r, g, b and out1 can also function as ports p5 2 Cp5 5 . set corresponding bit of the port p5 direction register (ad- dress 00cb 16 ) to 0 to specify these pins as osd output pins, or set it to 1 to specify it as a general-purpose port p5. the out2 can also function as port p1 0 . set bit 0 of the crt port control register (address 00ec 16 ) to 1 (output mode). after that, set bit 7 of the crt port control register to 1 to specify the pin as osd output pin, or set it to 0 to specify as port p1 0 . the input polarity of the h sync , v sync and output polarity of signals r, g, b, out1 and out2 can be specified with the crt port control register (address 00ec) . set a bit to 0 to specify positive polarity; set it to 1 to specify negative polarity (refer to figure 8.11.13). the crt port control register is shown in figure 8.10.17. fig. 8.10.17 crt port control register b 7b 6b 5b 4b 3b 2b 1b 0 c r t p o r t c o n t r o l r e g i s t e r ( c r t p ) [ a d d r e s s 0 0 e c 1 6 ] b n a m ef u n c t i o n sa f t e r r e s e t r w c r t p o r t c o n t r o l r e g i s t e r 0 h s y n c i n p u t p o l a r i t y s w i t c h b i t ( h s y c ) 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 10 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 2r / g / b o u t p u t p o l a r i t y s w i t c h b i t ( r / g / b ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 30 4 o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( o u t 1 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 5r s i g n a l o u t p u t s w i t c h b i t ( o p 5 ) 0 : r s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 6 g s i g n a l o u t p u t s w i t c h b i t ( o p 6 ) 0 : g s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 7b s i g n a l o u t p u t s w i t c h b i t ( o p 7 ) 0 : b s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( v s y c ) r w r w r w r w r w r w r w r w o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( o u t 2 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 71 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.10.9 raster coloring function an entire screen (raster) can be colored by setting the crt port con- trol register. since each of the r, g, b, out1, and out2 pins can be switched to raster coloring output, 8 raster colors can be obtained. when the character color/the character background color overlaps with the raster color, the color (r, g, b, out1, out2), specified for the character color/the character background color, takes priority of the raster color. this ensures that character color/character back- ground color is not mixed with the raster color. the example of raster coloring is shown in figure 8.10.18. fig. 8.10.18 example of raster coloring h s y n c a ' a o u t 1 r g b : c h a r a c t e r c o l o r r e d ( r + o u t 1 + o u t 2 ) : b o r d e r c o l o r b l a c k ( o u t 1 + o u t 2 ) : b a c k g r o u n d c o l o r m a g e n t a ( r + b + o u t 1 + o u t 2 ) : r a s t e r c o l o r b l u e ( b + o u t 1 + o u t 2 ) s i g n a l s a c r o s s a - a ' o u t 2 72 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig. 8.11.1 sequence at detecting software runaway detection 8.11 software runaway detect function this microcomputer has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation, the following processing is done. the cpu generates an undefined instruction decoding signal. the device is internally reset because of occurrence of the unde- fined instruction decoding signal. a as a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. note, however, that the software runaway detecting function cannot be invalid. a d h , a d l 0 1 , s 2 0 1 , s 1 p c h p c l p sa d h a d l p c ? ? : u n d e f i n e d i n s t r u c t i o n d e c o d e ? u n d e f i n e d i n s t r u c t i o n d e c o d i n g s i g n a l o c c u r s . i n t e r n a l r e s e t s i g n a l o c c u r s . f s y n c a d d r e s s d a t a r e s e t s e q u e n c e 0 1 , sf f f e 1 6 f f f f 1 6 : i n v a l i d : p r o g r a m c o u n t e r s : s t a c k p o i n t e r p c a d l , a d h : j u m p d e s t i n a t i o n a d d r e s s o f r e s e t 73 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.12. reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the reset pin at low for 2 m s or more, then return is to high. then, as shown in figure 8.12.2, reset is released and the program starts form the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal state of microcomputer at reset are shown in figures 8.2.3 to 8.2.6. an example of the reset circuit is shown in figure 8.12.1. the reset input voltage must be kept 0.6 v or less until the power source voltage surpasses 4.5 v. fig. 8.12.2 reset sequence fig. 8.12.1 example of reset circuit p o w e r s o u r c e v o l t a g e 0 v r e s e t i n p u t v o l t a g e 0 v 4 . 5 v 0 . 6 v p o w e r o n v c c r e s e t v s s m i c r o c o m p u t e r 1 5 4 3 0 . 1 m f m 5 1 9 5 3 a l x i n f r e s e t i n t e r n a l r e s e t s y n c a d d r e s s d a t a 3 2 7 6 8 c o u n t o f x i n c l o c k c y c l e ( s e e n o t e 3 ) r e s e t a d d r e s s f r o m t h e v e c t o r t a b l e ? ? 0 1 , s 0 1 , s - 1 0 1 , s - 2 f f f e f f f f a d h , a d l ? ? ? ? ? a d l a d h n o t e s 1 : f ( x i n ) a n d f ( f ) a r e i n t h e r e l a t i o n : f ( x i n ) = 2 f ( f ) . 2 : a q u e s t i o n m a r k ( ? ) i n d i c a t e s a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e . 3 : i m m e d i a t e l y a f t e r a r e s e t , t i m e r 3 a n d t i m e r 4 a r e c o n n e c t e d b y h a r d w a r e . a t t h i s t i m e , f f 1 6 i s s e t i n t i m e r 3 a n d 0 7 1 6 i s s e t t o t i m e r 4 . t i m e r 3 c o u n t s d o w n w i t h f ( x i n ) / 1 6 , a n d r e s e t s t a t e i s r e l e a s e d b y t h e t i m e r 4 o v e r f l o w s i g n a l . 74 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 8.13 clock generating circuit the built-in clock generating circuit is shown in figure 8.13.3. when the stp instruction is executed, the internal clock f stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in the timer 4. select f(x in )/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to 0 before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before ex- ecution of the stp instruction). the oscillator restarts when external interrupt is accepted. however, the internal clock f keeps its high until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. when the wit instruction is executed, the internal clock f stops in the high but the oscillator continues running. this wait state is re- leased when an interrupt is accepted (see note). since the oscillator does not stop, the next instruction can be executed at once. when returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to 1 before executing the stp or the wit instructions. note: in the wait mode, the following interrupts are invalid. ? v sync interrupt ? osd interrupt ? all timers interrupts using tim2 and tim3 pins input as count source ? all timers interrupts using f(x in )/2 as count source ? all timers interrupts using f(x in )/4092 as count source ? f(x in )/4096 interrupt ? multi-master i 2 c-bus interface interrupt a circuit example using a ceramic resonator (or a quartz-crystal os- cillator) is shown in figure 8.13.1. use the circuit constants in accor- dance with the resonator manufactures recommended values. a cir- cuit example with external clock input is shown in figure 8.13.2. in- put the clock to the x in pin, and open the x out pin. fig. 8.13.1 ceramic resonator circuit example fig. 8.13.2 external clock input circuit example x in x out c in microcomputer c out x in microcomputer vcc vss external oscillation circuit fig. 8.13.3 clock generating circuit block diagram i n t e r r u p t r e q u e s t i n t e r r u p t d i s a b l e f l a g i r e s e t s q r s t p i n s t r u c t i o n s q r w i t i n s t r u c t i o n s q r s t p i n s t r u c t i o n r e s e t i n t e r n a l c l o c k f 1 / 2 1 / 8 t i m e r 3 t i m e r 4 x o u t x i n t 3 4 m 0 t 3 4 m 2 s e l e c t i o n g a t e : c o n n e c t e d t o b l a c k s i d e a t r e s e t . t 3 4 m : t i m e r 3 4 m o d e r e g i s t e r 75 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 reset vss vcc circuit example 1 reset vss vcc circuit example 2 note : make the level change from ??to ??at the point at which the power source voltage exceeds the specified voltage. 8.14 display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, an rc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation cir- cuit is selected by setting bits 0 and 1 of the crt clock selection register (address 00ed 16 ). 8.16 addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 76 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 power source voltage v cc input voltage cnv ss input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 2 , osc1, x in , ______ h sync , v sync , reset output voltage p1 0 Cp1 4 , p2 0 Cp1 7 , p3 0 , p3 1 , p4 0 , p4 1 , r, g, b, out1, da x out , osc2 output voltage p0 0 Cp0 7 , p6 0 Cp6 3 circuit current r, g, b, out1, p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 , p3 1 , da circuit current r, g, b, out1, p0 6 , p0 7 , p1 0 , p2 0 Cp2 3 , p3 0 , p3 1 , p4 0 , p4 1 , da circuit current p1 1 Cp1 4 circuit current p0 0 Cp0 7 , p6 0 Cp6 3 circuit current p2 4 Cp2 7 power dissipation operating temperature storage temperature symbol v cc , av cc v i v i v o v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg 10. absolute maximum ratings conditions all voltages are based on v ss . output transistors are cut off. parametear t a = 25 c unit v v v v v ma ma ma ma ma mw c c ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to 13 0 to 1 (see note 1) 0 to 2 (see note 2) 0 to 6 (see note 2) 0 to 1 (see note 2) 0 to 10 (see note 3) 550 C10 to 70 C40 to 125 power source voltage (see note 4), during cpu, osd operation power source voltage high input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7, ______ s in , s clk , h sync , v sync , reset, x in , osc1, tim2, tim3, int1Cint3 high input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) low input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 2 low input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) low input voltage (see note 6) ______ h sync , v sync , reset, tim2, tim3, int1Cint3, x in , osc1, s in , s clk high average output current (see note 1) r, g, b, out1, da, p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 , p3 1 low average output current (see note 2) r, g, b, out1, da, p1 0 , p2 0 Cp2 3 , p3 0 , p3 1, p4 0 , p4 1 low average output current (see note 2) p1 1 Cp1 4 low average output current (see note 2) p0 0 Cp0 7 , p6 0 Cp6 3 low average output current (see note 3) p2 4 Cp2 7 oscillation frequency (for cpu operation) (see note 5) x in oscillation frequency (for osd) osc1 input frequency tim2, tim3 input frequency s clk input frequency scl1, scl2 limits min. 4.5 0 0.8v cc 0.7v cc 0 0 0 7.9 5.0 typ. 5.0 0 8.0 max. 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 6 1 10 8.1 8.0 100 1 400 v v v v v v v ma ma ma ma ma mhz mhz khz mhz khz 11. recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) v cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 i ol4 f(x in ) fosc f hs1 f hs2 f hs3 symbol parameter unit 77 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 power source current high output voltage r, g, b, out1, da, p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 , p3 1 low output voltage r, g, b, out1, da, p1 0 , p2 0 Cp2 3 , p3 0 , p3 1 , p4 0 , p4 1 low output voltage p2 4 Cp2 7 low output voltage p1 1 Cp1 4 low output voltage p0 0 Cp0 7 , p6 0 Cp6 3 hysteresis ______ reset hysteresis (see note 6) h sync , v sync , tim2, tim3, int1Cint3, scl1, scl2, sda1, sda2, s in , s clk high input leak current ______ reset, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 2 , h sync , v sync low input leak current ______ reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 2 , p6 0 Cp6 3 , h sync , v sync high input leak current p0 0 Cp0 7 , p6 0 Cp6 3 i 2 c-busbus switch connection resistor (between scl1 and scl2, sda1 and sda2) max. 20 40 40 60 300 0.4 3.0 0.4 0.6 0.4 0.7 1.3 5 5 10 130 limits min. 2.4 12. electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) i cc v oh v ol v t+ C v tC i izh i izl i ozh r bs typ. 10 20 20 30 0.5 0.5 symbol parameter test conditions unit system operation stop mode v cc = 5.5 v, f(x in ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v v cc = 4.5 v i ol = 0.5 ma v cc = 5.0 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v i = 12 v v cc = 4.5 v osd off osd on osd off osd on test circuit v cc = 5.5 v, f(x in ) = 4 mhz v cc = 5.5 v, f(x in ) = 8 mhz ma m a v v v m a m a m a w 1 4 2 3 5 notes 1: the total current that flows out of the ic must be 20 ma or less. 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. 4: connect 0.1 m f or more capacitor externally between the power source pins v cc Cv ss so as to reduce power source noise. also connect 0.1 m f or more capacitor externally between the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p1 5 , p3 2 Cp3 5 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 Cp1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p4 0 Cp4 2 have the hysteresis when these pins are used as serial i/o pins. 7: pin names in each parameter is described as below. (1) dedicated pins: dedicated pin names. (2) duble-/triple-function ports ? when the same limits: i/o port name. ? when the limits of functins except ports are different from i/o port limits: function pin name. i ol = 3 ma i ol = 6 ma 6 78 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 fig.12.1 measure circuits 1 3 5 2 4 6 v s s v c c v v o h o r v o l i o h o r i o l 4 . 5 v e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n t o h i g h l e v e l w h e n m e a s u r i n g v o h a n d t o l o w l e v e l w h e n m e a s u r i n g v o l , e a c h p i n i s m e a s u r e d . v s s v c c 5 . 0 v e a c h i n p u t p i n v s s v c c v b s 4 . 5 v s c l 1 o r s d a 1 i b s a r b s = v b s / i b s s c l 2 o r s d a 2 r b s v s s v c c 5 . 5 v e a c h i n p u t p i n a i i z h o r i i z l v s s v c c 5 . 5 v a e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n o f f s t a t e , e a c h p i n i s m e a s u r e d i oz h 1 2 v a v s s v c c x i n x o u t o s c 1 o s c 2 i c c 8 . 0 0 m h z + p o w e r s o u r c e v o l t a g e p i n v c c i s m a d e t h e o p e r a t i o n s t a t e a n d i s m e a s u r e d t h e c u r r e n t , w i t h a c e r a m i c r e s o n a t o r . 79 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 13. a-d comparison characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = 25 c, unless otherwise noted) resolution absolute accuracy max. 6 2 bits lsb min. 0 limits unit test conditions parameter symbol typ. 1 14. multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd; sta t low t r t hd; dat t high t f t su; dat t su; sta t su; sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 m s m s m s ns m s m s ns ns m s m s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig.14.1 definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 sda scl p t buf s t hd ; sta t low t r t hd ; dat t high t f t su ; dat t su ; sta sr p t su ; sto t hd ; sta s sr p : start condition : restart condition : stop condition 80 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 15. prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. product m37212efsp m37212effp name of programming adapter pca7406 pca7420 the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 15.1 is recommended to verify programming. fig. 15.1 programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150? exceeding 100 hours. 81 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 16. data required for mask orders the following are necessary when ordering a mask rom produc- tion: ? mask rom order confirmation form ? mark specification form ? data to be written to rom, in eprom form (32-pin dip type 27c101, three identical copies) or fdk 82 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 17. mask confirmation form (1/3) gzzCsh55C23b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m4-xxxsp mitsubishi electric ] customer company name date issued ] 1. confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. (1) set ff 16 in the shaded area. mask rom number receipt date: section head signature supervisor signature tel ( ) date : issuance signature note : please fill in all items marked ] . submitted by supervisor checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) eprom address product nameascii code: 'm37212m4-' 2 7 c 1 0 1 0000 16 000f 16 1234567890123456 1 23456789012345 6 1 23456789012345 6 1234567890123456 data rom(16k) character rom2-b 10800 16 10fff 16 ffff 16 c000 16 10000 16 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 107ff 16 character rom1-b character rom2-a character rom1-a 11000 16 117ff 16 11800 16 11fff 16 12000 16 1ffff 16 83 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (2/3) gzzCsh55C23b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m4-xxxsp mitsubishi electric addresses 0000 16 to 000f 16 store the product name. ascii codes m37212m4- are listed on the right. the addresses and data are in hexadecimal notation. note : if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. please make sure the data is written correctly. address 0000 16 m = 4d 16 0001 16 3 = 33 16 0002 16 7 = 37 16 0003 16 2 = 32 16 0004 16 1 = 31 16 0005 16 2 = 32 16 0006 16 m = 4d 16 0007 16 4 = 34 16 address 0008 16 C = 2d 16 0009 16 ff 16 000a 16 ff 16 000b 16 ff 16 000c 16 ff 16 000d 16 ff 16 000e 16 ff 16 000f 16 ff 16 ordering by floppy disk we will produce masks based on the mask files generated by the mask file generating utility. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this mask file. thus, extreme care must be taken to verify the mask file in the submitted floppy disk. the submitted floppy disk must be 3.5-inch 2hd type and dos/v format. and the number of the mask files must be 1 in one floppy disk. file code (hexadecimal notation) mask file name .msk (equal or less than eight characters) ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill the appropriate mark specification form (52p4b for m37212m4-xxxsp) and attach to the mask rom confirmation form. ] 3. comments (2) write the ascii codes that indicate the product name of m37212m4C to addresses 0000 16 to 000f 16 . 84 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (3/3) gzzCsh55C23b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m4-xxxsp mitsubishi electric inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. the structure of character rom ( divided into 12 5 16 dots font) example character code 1a 16 101a0 16 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 1 1 1 2 2 3 4 4 4 0 0 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 109a0 16 109af 16 character rom1 character rom2 f 16 0 16 4 16 a 16 1 16 04 16 a 16 1 16 1 16 0 16 0 16 f 16 0 16 0 16 0 16 0 16 0 16 (note) write the character code "00 16 " to "7f 16 " to addresses 10000 16 to 10fff 16. write the character code "80 16 " to "ff 16 " to addresses 11000 16 to 11fff 16. example example to to 85 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (1/3) gzzCsh55C24b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m6-xxxsp/fp mitsubishi electric mask rom number receipt date: section head signature supervisor signature ] customer company name tel ( ) date : date issued issuance signature note : please fill in all items marked ] . submitted by supervisor ] 1. confirmation specify the name of the product being ordered. three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) (1) set ff 16 in the shaded area. microcomputer name : m37212m6-xxxsp m37212m6-xxxfp eprom address product nameascii code: 'm37212m6-' 2 7 c 1 0 1 0000 16 000f 16 12345678901234567 1 234567890123456 7 1 234567890123456 7 12345678901234567 data rom(24k) character rom2-b 10800 16 10fff 16 ffff 16 a000 16 10000 16 12345678901234567 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 12345678901234567 107ff 16 character rom1-b character rom2-a character rom1-a 11000 16 117ff 16 11800 16 11fff 16 12000 16 1ffff 16 86 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (2/3) gzzCsh55C24b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m6-xxxsp/fp mitsubishi electric addresses 0000 16 to 000f 16 store the product name. ascii codes m37212m6- are listed on the right. the addresses and data are in hexadecimal notation. note : if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. please make sure the data is written correctly. address 0000 16 m = 4d 16 0001 16 3 = 33 16 0002 16 7 = 37 16 0003 16 2 = 32 16 0004 16 1 = 31 16 0005 16 2 = 32 16 0006 16 m = 4d 16 0007 16 6 = 36 16 address 0008 16 C = 2d 16 0009 16 ff 16 000a 16 ff 16 000b 16 ff 16 000c 16 ff 16 000d 16 ff 16 000e 16 ff 16 000f 16 ff 16 ordering by floppy disk we will produce masks based on the mask files generated by the mask file generating utility. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this mask file. thus, extreme care must be taken to verify the mask file in the submitted floppy disk. the submitted floppy disk must be 3.5-inch 2hd type and dos/v format. and the number of the mask files must be 1 in one floppy disk. file code (hexadecimal notation) mask file name .msk (equal or less than eight characters) ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill the appropriate mark specification form (52p4b for m37212m6-xxxsp , 80p6n for m37212m6-xxxfp) and attach to the mask rom confirmation form. ] 3. comments (2) write the ascii codes that indicate the product name of m37212m6C to addresses 0000 16 to 000f 16 . 87 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (3/3) gzzCsh55C24b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m6-xxxsp/fp mitsubishi electric inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. the structure of character rom(divided into 12 5 16 dots font) example character code 1a 16 101a0 16 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 1 1 1 2 2 3 4 4 4 0 0 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 109a0 16 109af 16 character rom1 character rom2 f 16 0 16 4 16 a 16 1 16 04 16 a 16 1 16 1 16 0 16 0 16 f 16 0 16 0 16 0 16 0 16 0 16 (note) write the character code "00 16 " to "7f 16 " to addresses 10000 16 to 10fff 16. write the character code "80 16 " to "ff 16 " to addresses 11000 16 to 11fff 16 . example example to to 88 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 gzzCsh55C42b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m8-xxxsp mitsubishi electric mask rom number receipt date: section head signature supervisor signature ] customer company name tel ( ) date : date issued issuance signature note : please fill in all items marked ] . submitted by supervisor ] 1. confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) (1) set ff 16 in the shaded area. eprom address product nameascii code: 'm37212m8-' 2 7 c 1 0 1 character rom2-b character rom1-b character rom2-a character rom1-a 0000 16 000f 16 12345678901234567 1 234567890123456 7 1 234567890123456 7 12345678901234567 data rom(32k) 10800 16 10fff 16 ffff 16 8000 16 10000 16 12345678901234567 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 12345678901234567 107ff 16 11000 16 117ff 16 11800 16 11fff 16 12000 16 1ffff 16 (1/3) 89 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (2/3) gzzCsh55C42b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m8-xxxsp addresses 0000 16 to 000f 16 store the product name. ascii codes m37212m8- are listed on the right. the addresses and data are in hexadecimal notation. note : if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. please make sure the data is written correctly. address 0000 16 m = 4d 16 0001 16 3 = 33 16 0002 16 7 = 37 16 0003 16 2 = 32 16 0004 16 1 = 31 16 0005 16 2 = 32 16 0006 16 m = 4d 16 0007 16 8 = 38 16 address 0008 16 C = 2d 16 0009 16 ff 16 000a 16 ff 16 000b 16 ff 16 000c 16 ff 16 000d 16 ff 16 000e 16 ff 16 000f 16 ff 16 ordering by floppy disk we will produce masks based on the mask files generated by the mask file generating utility. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this mask file. thus, extreme care must be taken to verify the mask file in the submitted floppy disk. the submitted floppy disk must be 3.5-inch 2hd type and dos/v format. and the number of the mask files must be 1 in one floppy disk. file code (hexadecimal notation) mask file name .msk (equal or less than eight characters) ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill the appropriate mark specification form (52p4b for m37212m8-xxxsp) and attach to the mask rom confirmation form. ] 3. comments (2) write the ascii codes that indicate the product name of m37212m8C to addresses 0000 16 to 000f 16 . 90 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 (3/3) gzzCsh55C42b < 91a0 > 740 family mask rom confirmation form single-chip microcomputer m37212m8-xxxsp mitsubishi electric inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. the structure of character rom (divided into 12 5 16 dots font) example character code 1a 16 101a0 16 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 1 1 1 2 2 3 4 4 4 0 0 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 109a0 16 109af 16 character rom1 character rom2 f 16 0 16 4 16 a 16 1 16 04 16 a 16 1 16 1 16 0 16 0 16 f 16 0 16 0 16 0 16 0 16 0 16 (note) write the character code "00 16 " to "7f 16 " to addresses 10000 16 to 10fff 16. write the character code "80 16 " to "ff 16 " to addresses 11000 16 to 11fff 16. example example to to 91 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 18. mark specification form 92 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 1 80 65 40 64 41 25 24 mitsubishi product number (6-digit, or 7-digit) 1 80 65 40 64 41 25 24 customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name notes 1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 14 alphanumeric char- acters for capital letters, hyphens, commas, periods and so on. 4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required 80p6n (80-pin qfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi ic catalog name and the special mark (if neede d). a. standard mitsubishi mark c. special mark required b. customers parts number + mitsubishi ic catalog name mitsubishi ic catalog name notes1 :if special mark is to be printed, indicate the desired lay- out of the mark in the left figure. the layout will be duplicated technically as close as possible. mitsubishi product number (6-digit, or 7-digit) and mask rom number (3-digit) are always marked for sorting the products. 2 : if special character fonts (e,g., customers trade mark logo) must be used in special mark, check the box be- low. for the new special character fonts, a clean font original (ideally logo drawing) must be submitted. special character fonts required 1 80 65 40 64 41 25 24 93 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 19. one time prom version m37212efsp/fp marking m37212efsp xxxxxxx xxxxxxx is mitsubishi lot number m37212effp xxxxxxx xxxxxxx is mitsubishi lot number 94 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 20. appendix pin configuration (top view) outline 52p4b 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 p 4 1 / s c l k / a - d 6 x o u t h s y n c v s y n c p 6 0 / p w m 0 p 6 1 / p w m 1 p 6 2 / p w m 2 p 6 3 / p w m 3 p 0 0 / p w m 4 p 0 1 / p w m 5 p 4 0 / s o u t ( / i n ) / a - d 7 d a p 3 5 / i n t 2 / a - d 4 p 3 4 / i n t 1 p 3 3 / t i m 3 p 3 2 / t i m 2 p 2 4 p 2 5 c n v s s x i n v s s p 5 2 / r p 5 3 / g p 5 4 / b p 5 5 / o u t 1 p 2 0 p 2 1 p 2 2 p 1 0 / o u t 2 / a - d 8 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 p 1 5 / i n t 3 / a - d 1 p 1 6 / a - d 2 p 3 0 p 3 1 r e s e t o s c 1 / p 3 6 o s c 2 / p 3 7 v c c p 1 7 / a - d 3 p 0 2 / p w m 6 p 0 3 / p w m 7 p 4 2 / s i n / a - d 5 p 2 6 p 2 7 p 2 3 p 0 4 p 0 5 p 0 6 p 0 7 2 2 2 3 2 4 2 5 2 6 3 1 3 0 2 9 2 8 2 7 m 3 7 2 1 2 m 4 / m 6 / m 8 - x x x s p , m 3 7 2 1 2 e f s p 95 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 outline 80p6n-a p 0 7 5 5 4 3 p 1 0 / o u t 2 / a - d 8 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 p 1 5 / i n t 3 / a - d 1 p 1 6 / a - d 2 p 3 0 p 3 1 r e s e t o s c 1 / p 3 6 o s c 2 / p 3 7 v c c p 1 7 / a - d 3 h s y n c v s y n c p 6 0 / p w m 0 p 6 1 / p w m 1 p 6 2 / p w m 2 p 6 3 / p w m 3 p 0 0 / p w m 4 p 0 1 / p w m 5 p 0 2 / p w m 6 p 0 3 / p w m 7 x o u t v s s p 4 1 / s c l k / a - d 6 p 4 0 / s o u t ( / i n ) / a - d 7 d a p 3 5 / i n t 2 / a - d 4 p 3 4 / i n t 1 p 3 3 / t i m 3 p 3 2 / t i m 2 p 2 4 p 2 5 p 4 2 / s i n / a - d 5 c n v s s x i n p 2 6 p 2 7 p 5 2 / r p 5 3 / g p 5 4 / b p 5 5 / o u t 1 p 2 0 p 2 1 p 2 2 p 2 3 p 0 4 p 0 5 p 0 6 2 8 4 0 3 9 3 7 3 8 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 7 2 6 2 5 5 1 4 1 4 4 4 5 4 6 4 7 4 8 5 0 5 8 5 2 5 9 5 7 5 6 6 0 6 1 6 3 6 2 4 2 4 9 n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c 8 1 2 3 4 5 6 7 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 4 2 3 2 2 2 1 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 m 3 7 2 1 2 m 6 - x x x f p , m 3 7 2 1 2 e f f p n c 6 4 5 4 5 3 96 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 memory map 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 6 b 7 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 0 6 0 0 1 6 1 1 f f f 1 6 1 f f f f 1 6 o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) 0 1 7 f 1 6 0 1 b f 1 6 1 0 0 0 0 1 6 o s d r o m ( 8 k b y t e s ) s f r a r e a i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e z e r o p a g e n o t e : r e f e r t o t a b l e 8 . 1 0 . 3 o s d r a m . 0 1 0 0 1 6 0 0 b f 1 6 n o t u s e d a 0 0 0 1 6 n o t u s e d c 0 0 0 1 6 n o t u s e d m 3 7 2 1 2 m 6 - x x x s p / f p r a m ( 3 8 4 b y t e s ) m 3 7 2 1 2 m 4 - x x x s p r a m ( 3 2 0 b y t e s ) m 3 7 2 1 2 m 6 - x x x s p / f p r o m ( 2 4 k b y t e s ) m 3 7 2 1 2 m 4 - x x x s p r o m ( 1 6 k b y t e s ) n m 3 7 2 1 2 m 4 / m 8 - x x x s p , m 3 7 2 1 2 m 6 - x x x s p / f p 97 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 6 b 7 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 0 6 0 0 1 6 1 1 f f f 1 6 1 f f f f 1 6 o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) m 3 7 2 1 2 e f s p r a m ( 1 2 8 0 b y t e s ) 0 8 0 0 1 6 1 0 0 0 0 1 6 o s d r o m ( 8 k b y t e s ) 0 2 c 0 1 6 s f r a r e a i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e z e r o p a g e n o t u s e d n o t e : r e f e r t o t a b l e 8 . 1 0 . 3 o s d r a m 0 2 1 7 1 6 0 2 1 b 1 6 r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 0 1 0 0 1 6 0 0 b f 1 6 0 5 f f 1 6 n o t u s e d 0 2 e 0 1 6 m 3 7 2 1 2 m 8 - x x x s p r a m ( 5 7 6 b y t e s ) 0 1 f f 1 6 n o t u s e d n o t u s e d 0 3 3 f 1 6 2 p a g e r e g i s t e r m 3 7 2 1 2 e f s p r o m ( 6 2 k b y t e s ) m 3 7 2 1 2 m 8 - x x x s p r o m ( 3 2 k b y t e s ) 8 0 0 0 1 6 n m 3 7 2 1 2 m 8 - x x x s p , m 3 7 2 1 2 e f s p / f p 98 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 memory map of special function register (sfr) n s f r a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) d 0 1 6 d 1 1 6 d 2 1 6 d 3 1 6 d 4 1 6 d 5 1 6 d 6 1 6 d 7 1 6 d 8 1 6 d 9 1 6 d a 1 6 d b 1 6 d c 1 6 d d 1 6 d e 1 6 d f 1 6 c 0 1 6 c 1 1 6 c 2 1 6 c 3 1 6 c 4 1 6 c 5 1 6 c 6 1 6 c 7 1 6 c 8 1 6 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 c a 1 6 a d d r e s s p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( d 5 ) d a - h r e g i s t e r ( d a - h ) d a - l r e g i s t e r ( d a - l ) p w m 0 r e g i s t e r ( p w m 0 ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( d 1 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m 2 r e g i s t e r ( p w m 2 ) p w m 3 r e g i s t e r ( p w m 3 ) p w m 4 r e g i s t e r ( p w m 4 ) p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) b 7 b 0 b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t ? 0 0 1 6 b 7 b 0 ? 0 0 1 6 ? 0 0 1 6 0? ? ? ?00 s e r i a l i / o m o d e r e g i s t e r ( s m ) s e r i a l i / o r e g i s t e r ( s i o ) 0 0 1 6 p o r t p 6 ( p 6 ) p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) 0 p 5 2 s e l 00 p 5 3 s e l p 5 4 s e l p 5 5 s e l p 5 2 p 5 3 p 5 4 p 5 5 p 3 1 dp 3 0 d ? 0 ? 0 0 0 ?? 0 p w 0 p w 1 p w 2 p w 3 p w 4 p w 5 p w 6 p w 7 p n 2 p n 3 p n 4 ? 0 0 ? ? ? ? ? ? ? ? ? ? 0 0 1 6 0 0 1 6 0 f 1 6 s a d 0 s a d 1 s a d 2 s a d 3 s a d 4 s a d 5 s a d 6 r b w l r b a d 0 a a s a l p i n b b t r x m s t b c 0 b c 1 b c 2 e s o a l s b s e l 0 b s e l 1 1 0 b i t s a d d 1 d 2 d 3 d 4 d 5 d 6 d 7d 0 ? ? 0 0 1 6 0 0 1 6 s m 0 s m 1 s m 2 s m 3 s m 5 s m 6 0 c c r 0 c c r 1 c c r 2 c c r 3 c c r 4 a c k f a s t m o d e a c k b i t ? 0 0 1 6 0 0 1 6 ? 0 0 ? 0 0 0 1 0 : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( d 4 ) p n 0 p n 1 p 4 1 dp 4 0 d p 4 1p 4 0 p 6 1p 6 0 p 6 2 0 ? 0 0 0 ?? 0 0 0 1 6 0 f 1 6 ? p 6 3 11 1 1 99 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e 7 1 6 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 c r t c o n t r o l r e g i s t e r ( c c ) c r t p o r t c o n t r o l r e g i s t e r ( c r t p ) a - d m o d e r e g i s t e r ( a d m ) a - d c o n t r o l r e g i s t e r ( a d c ) t i m e r 1 ( t 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 ( c v 2 ) c o l o r r e g i s t e r 0 ( c o 0 ) c o l o r r e g i s t e r 1 ( c o 1 ) c h a r a c t e r s i z e r e g i s t e r ( c s ) b o r d e r s e l e c t i o n r e g i s t e r ( m d ) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h r ) v e r t i c a l p o s i t i o n r e g i s t e r 1 ( c v 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) p w m 5 r e g i s t e r ( p w m 5 ) i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) c o l o r r e g i s t e r 2 ( c o 2 ) c o l o r r e g i s t e r 3 ( c o 3 ) c r t c l o c k s e l e c t i o n r e g i s t e r ( c k ) c p u m o d e r e g i s t e r ( c m ) b 7 b 0 c c 0 c c 1 c c 2 t 3 4 m 0 c m 2 t m 1 r t m 2 r t m 3 r t m 4 r o s d r v s c r i t 3 r c k 0 m s r i t 1 r i t 2 r s 1 r t m 1 e t m 2 e t m 3 e t m 4 e o s d e v s c e i t 3 e i t 1 e i t 2 e s 1 e m s e b 7 b 0 f f 1 6 0 7 1 6 f f 1 6 0 7 1 6 ? ? ? 00 1 0 0 11 11 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 fc 1 6 0 0 1 6 0 0 1 6 0 0 1 6 p w m 6 r e g i s t e r ( p w m 6 ) p w m 7 r e g i s t e r ( p w m 7 ) i i c r r e3 r e4 h r 0 h r 1 h r 2 h r 3 h r 4 h r 5 c v 1 0 c s 1 0 c s 1 1 c s 2 0 c s 2 1 m d 1 0 m d 2 0 c c 7 v s y c r / g / b o u t 2 o p 5 o u t 1 o p 6h s y c a d m0 a d c0 0 0 1 6 0 00 0?0 ? 0 0 00 ??? ? 0 0 0 1 6 0 0 1 6 n s f r a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 i i c e 00 0 0 r e5 t 3 4 m 1 t 3 4 m 2 t 3 4 m 3 t 3 4 m 4 t 3 4 m 5 t 1 2 m 0 t 1 2 m 1 t 1 2 m 2 t 1 2 m 3 t 1 2 m 4 0 a d c1 a d c2 a d c3 a d c4 a d c5 a d m1 a d m2 a d m4 00 c k0 c k1 o p 7 c o 3 1 c o 3 2 c o 3 3 c o 3 5c o 3 4 c o 3 6 c o 3 7 c o 2 1 c o 2 2 c o 2 3 c o 2 5c o 2 4 c o 2 6 c o 2 7 c o 1 1 c o 1 2 c o 1 3 c o 1 5c o 1 4 c o 1 6 c o 1 7 c o 0 1 c o 0 2 c o 0 3 c o 0 5c o 0 4 c o 0 6 c o 0 7 c v 1 1 c v 1 2 c v 1 3 c v 1 4 c v 1 5 c v 1 6 c v 2 0 c v 2 1 c v 2 2 c v 2 3 c v 2 4 c v 2 5 c v 2 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 ? 00 000 0 0 0 0 1 6 ? 0 0 1 6 ? ?? ??? ? 0 ? ?? ??? ? 0 0000 ?00 0000 0 100 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 b 7b 0b 7b 0 2 1 7 1 6 2 1 8 1 6 2 1 9 1 6 2 1 b 1 6 2 1 a 1 6 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) r c r 1r c r 0 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 0 1 6 n 2 p a g e r e g i s t e r a r e a ( a d d r e s s e s 2 1 7 1 6 t o 2 1 b 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 n o t e : o n l y m 3 7 2 1 2 m 8 - x x x s p a n d m 3 7 2 1 2 e f s p / f p h a v e 2 p a g e r e g i s t e r . 101 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i z c d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 102 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e b i t a t t r i b u t e s ( n o t e 1 ) ( n o t e 2 ) b i t p o s i t i o n 2 : b i t a t t r i b u t e s t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : b i t i n w h i c h n o t h i n g i s a s s i g n e d n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 0 a f t e r r e s e t r e l e a s e 1 1 a f t e r r e s e t r e l e a s e i n d e t e r m i n a t e i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e r e a d e n a b l e d r e a d d i s a b l e d r r r e a d w r i t e e n a b l e d w r i t e d i s a b l e d 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . w w r i t e w ] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e rw c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m ef u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( s e e n o t e ) ( c m 2 ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 1 . 6 , 7 0 c l o c k s w i t c h b i t s ( c m 6 , c m 7 ) 0 0 : f ( x i n ) = 8 m h z 0 1 : f ( x i n ) = 1 2 m h z 1 0 : f ( x i n ) = 1 6 m h z 1 1 : d o n o t s e t b 7 b 6 c p u m o d e r e g i s t e r ( c p u m ) ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw rw r w rw < e x a m p l e > 103 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 addresses 00c1 16 , 00c3 16 , 00c5 16 address 00c7 16 b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 0 0 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 3 0 : port pi 3 input mode 1 : port pi 3 output mode 0 4 0 : port pi 4 input mode 1 : port pi 4 output mode 0 5 0 : port pi 5 input mode 1 : port pi 5 output mode 0 6 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw b 7b 6b 5b 4b 3b 2b 1b 0 p o r t p i d i r e c t i o n r e g i s t e r ( d i ) ( i = 3 , 4 ) [ a d d r e s s 0 0 c 7 1 6 , 00 c 9 1 6 ] b n a m e f u n c t i o n s a f t e r r e s e t r w p o r t p i d i r e c t i o n r e g i s t e r 00 : p o r t p i 0 i n p u t m o d e 1 : p o r t p i 0 o u t p u t m o d e 0 1 0 : p o r t p i 1 i n p u t m o d e 1 : p o r t p i 1 o u t p u t m o d e 0 p o r t p i d i r e c t i o n r e g i s t e r rw rw i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e i n d e t e r m i n a t e . r? 2 t o 7 104 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00cb 16 b 7b 6b 5b 4b 3b 2b 1b 0 po r t p 5 d i r e c t i o n r e g i s t e r ( d 5 ) [ a d d r e s s 0 0 c b 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e tr w p o r t p 5 d i r e c t i o n r e g i s t e r 0 , 10 r n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 2 0 : r s i g n a l o u t p u t 1 : p o r t p 5 2 o u t p u t 0 r w 3p o r t p 5 3 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 3 s e l ) 0 : g s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t 0 r w 4p o r t p 5 4 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 4 s e l ) 0 : b s i g n a l o u t p u t 1 : p o r t p 5 4 o u t p u t 0 r w 5p o r t p 5 5 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 5 s e l ) 0 : o u t 1 s i g n a l o u t p u t 1 : p o r t p 5 5 o u t p u t 0 r w 6 , 7 p o r t p 5 2 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 2 s e l ) i n d e t e r m i n a t e r n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . address 00d5 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) [ a d d r e s s 0 0 d 5 b a f t e r r e s e t rw p w m o u t p u t c o n t r o l r e g i s t e r 1 0 1 2 3 4 0 n a m ef u n c t i o n s d a , p w m c o u n t s o u r c e s e l e c t i o n b i t ( p w 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p p 6 0 / p w m 0 o u t p u t s e l e c t i o n b i t ( p w 2 ) 0 : p 6 0 o u t p u t 1 : p w m 0 o u t p u t p 6 1 / p w m 1 o u t p u t s e l e c t i o n b i t ( p w 3 ) 0 : p 6 1 o u t p u t 1 : p w m 1 o u t p u t p 6 2 / p w m 2 o u t p u t s e l e c t i o n b i t ( p w 4 ) 0 : p 6 2 o u t p u t 1 : p w m 2 o u t p u t 5 p 6 3 / p w m 3 o u t p u t s e l e c t i o n b i t ( p w 5 ) 0 : p 6 3 o u t p u t 1 : p w m 3 o u t p u t 6 p 0 0 / p w m 4 o u t p u t s e l e c t i o n b i t ( p w 6 ) 0 : p 0 0 o u t p u t 1 : p w m 4 o u t p u t d a / p n 4 s e l e c t i o n b i t ( p w 1 ) 0 : d a o u t p u t 1 : p n 4 o u t p u t 7 p 0 1 / p w m 5 o u t p u t s e l e c t i o n b i t ( p w 7 ) 0 : p 0 1 o u t p u t 1 : p w m 5 o u t p u t 0 0 0 0 0 0 0 1 6 ] rw rw rw rw rw rw rw rw 105 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00d6 16 address 00d7 16 address 00d8 16 b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 2 (pn) [address 00d6 16 ] b after reset rw pwm output control register 2 0 2 3 4 0 name functions da output polarity selection bit (pn2) 0 : positive polarity 1 : negative polarity pwm output polarity selection bit (pn3) da general-purpose output bit (pn4) 0 : output low 1 : output high 5 to 7 0 0 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : positive polarity 1 : negative polarity rw rw rw rw r p0 2 /pwm6 output selection bit (pn0) 0 : p0 2 1 : pwm6 output 1 0rw p0 3 /pwm7 output selection bit (pn1) 0 : p0 3 1 : pwm7 output b 7b 6b 5b 4b 3b 2b 1b 0 0 r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 d 8 1 6 ] b n a m e f u n c t i o n s 0 0 a f t e r r e s e t r w r r w b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) [ a d d r e s s 0 0 d 7 1 6 ] b f u n c t i o n sa f t e r r e s e trw i c d a t a s h i f t r e g i s t e r 0 t o 7 t h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a . i n d e t e r m i n a t e 2 n o t e : 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n a m e d 0 t o d 7 rw 106 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00d9 16 address 00da 16 b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 d 9 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : s l a v e r e c i e v e m o d e 0 1 : s l a v e t r a n s m i t m o d e 1 0 : m a s t e r r e c i e v e m o d e 1 1 : m a s t e r t r a n s m i t m o d e 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b u s f r e e 1 : b u s b u s y b u s b u s y f l a g ( b b ) 0 : i n t e r r u p t r e q u e s t i s s u e d 1 : n o i n t e r r u p t r e q u e s t i s s u e d i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n o t d e t e c t e d 1 : d e t e c t e d a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : a d d r e s s m i s m a t c h 1 : a d d r e s s m a t c h s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o g e n e r a l c a l l d e t e c t e d 1 : g e n e r a l c a l l d e t e c t e d g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l a s t b i t = 0 1 : l a s t b i t = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) b 7b 6b 5b 4b 3b 2b 1b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t 5a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s ( b s e l 0 , b s e l 1 ) b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 , s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s 0 0 d a 1 6 ] i 2 c c o n t r o l r e g i s t e r b n a m e f u n c t i o n s a f t e r r e s e t r w 2 r w r w r w r w r w 107 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00db 16 address 00dc 16 b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s 0 0 d b 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 t o 4 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 t o c c r 4 ) 7 5 6 s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e 0 s t a n d a r d c l o c k m o d e b n a m e f u n c t i o n s a f t e r r e s e t r w 0 0 0 a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . 0 : n o a c k c l o c k 1 : a c k c l o c k h i g h s p e e d c l o c k m o d e s e t u p d i s a b l e d s e t u p d i s a b l e d 0 0 t o 0 2 s e t u p d i s a b l e d 3 3 3 0 3 s e t u p d i s a b l e d 2 5 0 0 4 1 0 0 4 0 0 ( s e e n o t e ) 0 5 8 3 . 31 6 6 0 6 5 0 0 / c c r v a l u e 1 0 0 0 / c c r v a l u e . . . 1 7 . 2 3 4 . 5 1 d 1 6 . 63 3 . 3 1 e 1 6 . 1 3 2 . 3 1 f ( a t f = 4 m h z , u n i t : k h z ) n o t e : a t 4 0 0 k h z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 3 : 2 i n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 1 : 1 s e t u p v a l u e o f c c r 4 C c c r 0 r w r w r w r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 d c 1 6 ] bn a m ef u n c t i o n s s e r i a l i / o m o d e r e g i s t e r 0 , 1i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 0 1 : f ( x i n ) / 1 6 1 0 : f ( x i n ) / 3 2 1 1 : f ( x i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 s e r i a l i / o p o r t s e l e c t i o n b i t ( s m 3 ) 6 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0 : p 4 0 , p 4 1 1 : s o u t ( / i n ) , s c l k 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : l s b f i r s t 1 : m s b f i r s t 4 f i x t h i s b i t t o 0 . 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . a f t e r r e s e t rw 0 0 0 0 0 0rw rw rw r w rw rw 0r s e r i a l i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n . 1 : i n p u t s i g n a l f r o m s o u t p i n . 0 108 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00e0 16 addresses 00e1 16 and 00e2 16 address 00e4 16 b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6, 7 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0 nothing is assigned. these bits are write disable bits. when thses bits are read out, the values are 0. rw r b7 b6 b5 b4 b3 b2 b1 b0 vertical position register i (cvi) (i = 1 and 2) [addresses 00e1 16, 00e2 16 ] b name functions after reset r w vertical position register i 0 to 6 7 vertical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cvi : cvi0 to cvi6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r b7 b6 b5 b4 b3 b2 b1 b0 character size register (cs) [address 00e4 16 ] b name functions after reset r w character size register 0, 1 character size of block 1 selection bits (cs10, cs11) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. indeterminate 2,3 4 to 7 0 character size of block 2 selection bits (cs20,cs21) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw rw r 109 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00e5 16 addresses 00e6 16 to 00e9 16 b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out1 output border selection bit (md10) 0 : same output as r, g, b is output 1 : border output indeterminate 2 block 2 out1 output border selection bit (md20) 0 : same output as r, g, b is output 1 : border output indeterminate rw rw 0 3 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r 0 1 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r b 7b 6b 5b 4b 3b 2b 1b 0 c o l o r r e g i s t e r i ( c o i ) ( i = 0 t o 3 ) [ a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e t r w c o l o r r e g i s t e r i 0 0 r 1 g s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 2 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t i n d e t e r m i n a t e r w 2 r s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 3 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t r w 3 b s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 4 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 4 o u t 1 s i g n a l o u t p u t c o n t r o l b i t ( c o i 5 ) ( s e e n o t e s 1 , 2 ) 0 : c h a r a c t e r i s o u t p u t 1 : b l a n k i s o u t p u t r w 5 g s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 6 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 6 r s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 7 ) ( s e e n o t e 2 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 7 r w @ b s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 1 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . n o t e s 1 : w h e n b i t 5 = 0 a n d b i t 4 = 1 , t h e r e i s o u t p u t s a m e a s a c h a r a c t e r o r b o r d e r o u t p u t f r o m p i n o u t 1 . d o n o t s e t b i t 5 = 0 a n d b i t 4 = 0 . 2 : w h e n o n l y b i t 7 = 1 a n d b i t 5 0 , t h e r e i s o u t p u t f r o m p i n o u t 2 . i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e 110 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00ea 16 addresses 00ec 16 b7 b6 b5 b4 b3 b2 b1 b0 crt control register (cc) [address 00ea 16 ] b name functions after reset r w crt control register 0 all-blocks display control bit (cc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 6 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. block 2 display control bit (cc2) rw rw rw r 7 0 : p1 0 1 : out2 0 p1 0 /out2 pin switch bit (cc7) rw b 7b 6b 5b 4b 3b 2b 1b 0 c r t p o r t c o n t r o l r e g i s t e r ( c r t p ) [ a d d r e s s 0 0 e c 1 6 ] b n a m ef u n c t i o n sa f t e r r e s e t r w c r t p o r t c o n t r o l r e g i s t e r 0 h s y n c i n p u t p o l a r i t y s w i t c h b i t ( h s y c ) 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 10 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 2r / g / b o u t p u t p o l a r i t y s w i t c h b i t ( r / g / b ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 30 4 o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( o u t 1 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 5r s i g n a l o u t p u t s w i t c h b i t ( o p 5 ) 0 : r s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 6 g s i g n a l o u t p u t s w i t c h b i t ( o p 6 ) 0 : g s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 7b s i g n a l o u t p u t s w i t c h b i t ( o p 7 ) 0 : b s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( v s y c ) r w r w r w r w r w r w r w r w o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( o u t 2 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 111 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00ed 16 addresses 00ee 16 b 7b 6b 5b 4b 3b 2b 1b 0 c r t c l o c k s e l e c t i o n r e g i s t e r ( c k ) [ a d d r e s s 0 0 e d 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e t r w c r t c l o c k s e l e c t i o n r e g i s t e r 0 , 1 c r t c l o c k s e l e c t i o n b i t s ( c k 0 , c k 1 ) 0 s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r d i s p l a y , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n t a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 6 a n d p 3 7 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . ? a c e r a m i c r e s o n a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r ? a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r ( s e e n o t e ) 2 t o 7 0 0 0 0 0 0 0 b 1 t h e c l o c k f o r d i s p l a y i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . f u n c t i o n s 00 b 0 o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) / 1 . 5 n o t e : i t i s n e c e s s a r y t o c o n n e c t o t h e r c e r a m i c r e s o n a t o r o r q u a r t z - c r y s t a l o s c i l l a t o r a c r o s s t h e p i n s x 0 0 1 1 11 f i x t h e s e b i t s t o 0 . i n a n d x o u t . r w r w b 7b 6b 5b 4b 3b 2b 1b 0 a - d m o d e r e g i s t e r ( a d m ) [ a d d r e s s 0 0 e e 1 6 ] b a f t e r r e s e t rw a - d m o d e r e g i s t e r 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d m 0 t o a d m 2 ) n a m ef u n c t i o n s b 2 b 1 b 0 0 0 0 : a - d 1 0 0 1 : a - d 2 0 1 0 : a - d 3 0 1 1 : a - d 4 1 0 0 : a - d 5 1 0 1 : a - d 6 1 1 0 : a - d 7 1 1 1 : a - d 8 4 s t o r a g e b i t o f c o m p a r i s o n r e s u l t ( a d m 4 ) 0 : i n p u t v o l t a g e < r e f e r e n c e v o l t a g e 1 : i n p u t v o l t a g e > r e f e r e n c e v o l t a g e 0 i n d e t e r m i n a t e 0 3t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . rw r r 0 5 t o 7 n o t h i n g i s a s s i g n e d . t h i s b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r 112 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00ef 16 addresses 00f4 16 b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n t r o l r e g i s t e r ( a d c ) [ a d d r e s s 0 0 e f 1 6 ] b a f t e r r e s e t r w a - d c o n t r o l r e g i s t e r 0 t o 5 6 , 7 0 0 n a m ef u n c t i o n s d - a c o n v e r t e r s e t b i t s ( a d c 0 t o a d c 5 ) b 0 b 1 b 2 b 3 b 4 b 5 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e e d o u t , t h e v a l u e s a r e 0 . 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3 / 1 2 8 v c c : 5 / 1 2 8 v c c : 1 2 3 / 1 2 8 v c c : 1 2 5 / 1 2 8 v c c : 1 2 7 / 1 2 8 v c c : 1 / 1 2 8 v c c r w r b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r m o d e r e g i s t e r ( t 1 2 m ) [ a d d r e s s 0 0 f 4 1 6 ] b a f t e r r e s e t w t i m e r 1 2 m o d e r e g i s t e r 0 1 2 3 4 n a m e f u n c t i o n s t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t 1 2 m 0 ) 0 : f ( x i n ) / 1 6 1 : f ( x i n ) / 4 0 9 6 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t ( t 1 2 m 1 ) 0 : i n t e r r u p t c l o c k s o u r c e 1 : e x t e r n a l c l o c k f r o m t i m 2 p i n t i m e r 1 c o u n t s t o p b i t ( t 1 2 m 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 c o u n t s t o p b i t ( t 1 2 m 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 i n t e r n a l c o u n t s o u r c e s e l e c t i o n b i t 2 ( t 1 2 m 4 ) r 0 0 0 0 0 w r w r w r w r w r 0 : f ( x i n ) / 1 6 1 : t i m e r 1 o v e r f l o w 5 f i x t h i s b i t t o 0 . 0 w r 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r 0 113 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00f5 16 addresses 00f9 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) [ a d d r e s s 0 0 f 5 1 6 ] b a f t e r r e s e t rw t i m e r 3 4 m o d e r e g i s t e r 0 n a m e f u n c t i o n s t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 0 ) 0 rw 1 t i m e r 4 i n t e r n a l i n t e r r u p t c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 1 ) 0rw 2 3 t i m e r 3 c o u n t s t o p b i t ( t 3 4 m 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 4 c o u n t s t o p b i t ( t 3 4 m 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p 0 0 4 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 4 ) 0 : i n t e r n a l c l o c k s o u r c e 1 : f ( x i n ) / 2 0 5 t i m e r 3 e x t e r n a l c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 5 ) 0 : t i m 3 p i n i n p u t 1 : h s y n c p i n i n p u t 0 rw rw rw rw 0 : f ( x i n ) / 1 6 1 : e x t e r n a l c l o c k s o u r c e 0 : t i m e r 3 o v e r f l o w s i g n a l 1 : f ( x i n ) / 1 6 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) [ a d d r e s s 0 0 f 9 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 , 1 i n t 1 p o l a r i t y s w i t c h b i t ( r e 3 ) 20 0 3 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 4 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 5 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 6 0 7 0 0 i n t 2 p o l a r i t y s w i t c h b i t ( r e 4 ) i n t 3 p o l a r i t y s w i t c h b i t ( r e 5 ) n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . f i x t h i s b i t t o 0 . f i x t h i s b i t t o 0 . n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . r? r w r w r w r w r? r w 0 114 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00fb 16 addresses 00fc 16 b 7b 6b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e s e t rw c p u m o d e r e g i s t e r 0 , 1 2 3 t o 7 i n d e t e r m i n a t e i n d e t e r m i n a t e n a m ef u n c t i o n s f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( c m 2 ) ( s e e n o t e ) 1 0 : 0 p a g e 1 : 1 p a g e 1 0 0 c p u m o d e r e g i s t e r ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw r w n o t e : t h i s b i t i s s e t t o 1 a f t e r t h e r e s e t r e l e a s e . 1 1 1 f i x t h e s e b i t s t o 0 . b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1 t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2 t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4 o s d i n t e r r u p t r e q u e s t b i t ( o s d r ) 5 v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( i i c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ] 1 6 ] r r r r r r r r i n t 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 3 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 115 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00fd 16 addresses 00fe 16 b 7b 6 b 5 b 4b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 1 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 2 r ) 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( m s r ) 5 , 6 7 f i x t h i s b i t t o 0 . 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . 0 0 ] 0 ] 0 ] 0 ] 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 6 ] r r r r r ? r w 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0r ? n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bn a m ef u n c t i o n s rw i n t e r r u p t c o n t r o l r e g i s t e r 1 0 t i m e r 1 i n t e r r u p t e n a b l e b i t ( t m 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 t i m e r 2 i n t e r r u p t e n a b l e b i t ( t m 2 e ) 2 t i m e r 3 i n t e r r u p t e n a b l e b i t ( t m 3 e ) 3 4 o s d i n t e r r u p t e n a b l e b i t ( o s d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 0 rw rw rw rw rw r 7 t i m e r 4 i n t e r r u p t e n a b l e b i t ( t m 4 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 v s y n c i n t e r r u p t e n a b l e b i t ( v s c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw a f t e r r e s e t i n t 3 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 3 e ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t e n a b l e b i t ( i i c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d w 116 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 address 00ff 16 addresses 021b 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s i n t e r r u p t c o n t r o l r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 2 e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( m s e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d f i x t h i s b i t t o 0 . f i x t h e s e b i t s t o 0 . 0 00 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e i n d e t e r m i n a t e . a f t e r r e s e t 0 0 0 0 0 0 i n d e t e r m i n a t e rw rw rw rw rw r r w w r C 7 5 , 6 b 7b 6b 5b 4b 3b 2b 1b 0 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) [ a d d r e s s 0 2 1 b 1 6 ] ba f t e r r e s e t r o m c o r r e c t i o n e n a b l e r e g i s t e r 0 v e c t o r 1 e n a b l e b i t ( r c 0 ) n a m ef u n c t i o n s 0 : d i s a b l e d 1 : e n a b l e d 1 v e c t o r 2 e n a b l e b i t ( r c 1 ) 0 : d i s a b l e d 1 : e n a b l e d 4 t o 7 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 0 0 0 0 2 , 3 f i x t h e s e b i t s t o 0 . 0 rw rw rw r rw 117 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 21. package outline sdip52-p-600-1.78 weight(g) C jedec code 5.1 eiaj package code lead material alloy 42/cu alloy 52p4b plastic 52pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 C C C3.8C 0.4 0.5 0.6 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 C 1.778 C C 15.24 C 3.0 C C 0 e15 e e 5.5 e e 1 52 27 26 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d qfp80-p-1420-0.80 1.58 weight(g) e jedec code eiaj package code lead material alloy 42 80p6n-a plastic 80pin 14 5 20mm body qfp e 0.1 e ee 0.2 e e ee e e e e e symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.5 e e i 2 1.3 e e m d 14.6 e e m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.8 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 80 65 40 64 41 25 24 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers ? 1999 mitsubishi electric corp. new publication, effective sep. 1999. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan 119 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37212m4/m8Cxxxsp, m37212m6Cxxxsp/fp m37212efsp/fp mitsubishi microcomputers rev. 1.0 rev. rev. no. date 1.0 pdf first edition 9909 (1/1) revision description revision history m37212m4/m8-xxxsp, m37212m6-xxxsp/fp, m37212efsp/fp (rev.1.0) data sheet |
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